Design of A Low-Latency and Parallelizable SVD Dataflow Architecture on FPGA
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866915636343472128 |
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| author | Du, Fangqiang Chong, Sixuan Huang, Zixuan Qin, Rui Mi, Fengnan Hu, Caibao Chen, Jiangang |
| author_facet | Du, Fangqiang Chong, Sixuan Huang, Zixuan Qin, Rui Mi, Fengnan Hu, Caibao Chen, Jiangang |
| contents | Singular value decomposition (SVD) is widely used for dimensionality reduction and noise suppression, and it plays a pivotal role in numerous scientific and engineering applications. As the dimensions of the matrix grow rapidly, the computational cost increases significantly, posing a serious challenge to the efficiency of data analysis and signal processing systems, especially in time-sensitive scenarios involving large-scale datasets. Although various dedicated hardware architectures have been proposed to accelerate the computation of intensive SVD, many of these designs suffer from limited scalability and high consumption of on-chip memory resources. Moreover, they typically overlook the computational and data transfer challenges associated with SVD, making them unsuitable for real-time processing of large-scale data stream matrices in embedded systems. In this paper, we propose a Data Stream-Based SVD processing algorithm (DSB Jacobi), which significantly reduces on-chip BRAM usage while improving computational speed, offering a practical solution for real-time SVD computation of large-scale data streams. Compared to previous works, our experimental results indicate that the proposed method reduces on-chip RAM consumption by 41.5 percent and improves computational efficiency by a factor of 23. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2511_12461 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Design of A Low-Latency and Parallelizable SVD Dataflow Architecture on FPGA Du, Fangqiang Chong, Sixuan Huang, Zixuan Qin, Rui Mi, Fengnan Hu, Caibao Chen, Jiangang Distributed, Parallel, and Cluster Computing Signal Processing Singular value decomposition (SVD) is widely used for dimensionality reduction and noise suppression, and it plays a pivotal role in numerous scientific and engineering applications. As the dimensions of the matrix grow rapidly, the computational cost increases significantly, posing a serious challenge to the efficiency of data analysis and signal processing systems, especially in time-sensitive scenarios involving large-scale datasets. Although various dedicated hardware architectures have been proposed to accelerate the computation of intensive SVD, many of these designs suffer from limited scalability and high consumption of on-chip memory resources. Moreover, they typically overlook the computational and data transfer challenges associated with SVD, making them unsuitable for real-time processing of large-scale data stream matrices in embedded systems. In this paper, we propose a Data Stream-Based SVD processing algorithm (DSB Jacobi), which significantly reduces on-chip BRAM usage while improving computational speed, offering a practical solution for real-time SVD computation of large-scale data streams. Compared to previous works, our experimental results indicate that the proposed method reduces on-chip RAM consumption by 41.5 percent and improves computational efficiency by a factor of 23. |
| title | Design of A Low-Latency and Parallelizable SVD Dataflow Architecture on FPGA |
| topic | Distributed, Parallel, and Cluster Computing Signal Processing |
| url | https://arxiv.org/abs/2511.12461 |