Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
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arXiv
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| Main Authors: | , , , , , , , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866915622372245504 |
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| author | Chao, Zhiteng Wang, Yonghao Zhang, Xinyu Zhou, Jiaxin Hua, Tenghui Han, Husheng Yang, Tianmeng Mu, Jianan Yu, Bei Zhang, Rui Ye, Jing Li, Huawei |
| author_facet | Chao, Zhiteng Wang, Yonghao Zhang, Xinyu Zhou, Jiaxin Hua, Tenghui Han, Husheng Yang, Tianmeng Mu, Jianan Yu, Bei Zhang, Rui Ye, Jing Li, Huawei |
| contents | Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog. However, challenges remain in ensuring the quality of Verilog generation. Complex designs often fail in a single generation due to the lack of targeted decoupling strategies, and evaluating the correctness of decoupled sub-tasks remains difficult. While the chain-of-thought (CoT) method is commonly used to improve LLM reasoning, it has been largely ineffective in automating IC design workflows, requiring manual intervention. The key issue is controlling CoT reasoning direction and step granularity, which do not align with expert RTL design knowledge. This paper introduces VeriBToT, a specialized LLM reasoning paradigm for automated Verilog generation. By integrating Top-down and design-for-verification (DFV) approaches, VeriBToT achieves self-decoupling and self-verification of intermediate steps, constructing a Backtrack Tree of Thought with formal operators. Compared to traditional CoT paradigms, our approach enhances Verilog generation while optimizing token costs through flexible modularity, hierarchy, and reusability. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_13139 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT Chao, Zhiteng Wang, Yonghao Zhang, Xinyu Zhou, Jiaxin Hua, Tenghui Han, Husheng Yang, Tianmeng Mu, Jianan Yu, Bei Zhang, Rui Ye, Jing Li, Huawei Hardware Architecture Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog. However, challenges remain in ensuring the quality of Verilog generation. Complex designs often fail in a single generation due to the lack of targeted decoupling strategies, and evaluating the correctness of decoupled sub-tasks remains difficult. While the chain-of-thought (CoT) method is commonly used to improve LLM reasoning, it has been largely ineffective in automating IC design workflows, requiring manual intervention. The key issue is controlling CoT reasoning direction and step granularity, which do not align with expert RTL design knowledge. This paper introduces VeriBToT, a specialized LLM reasoning paradigm for automated Verilog generation. By integrating Top-down and design-for-verification (DFV) approaches, VeriBToT achieves self-decoupling and self-verification of intermediate steps, constructing a Backtrack Tree of Thought with formal operators. Compared to traditional CoT paradigms, our approach enhances Verilog generation while optimizing token costs through flexible modularity, hierarchy, and reusability. |
| title | Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2511.13139 |