Imagen de Portada

Coliseum project: Correlating climate change data with the behavior of heritage materials

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Cormier, A, Roqui, David, Surma, Fabrice, Labouré, Martin, Vallet, Jean-Marc, Guillon, Odile, Grozavu, N, Bourgès, Ann
Formato:	Preprint
Publicado:	2025
Materias:	Hardware Architecture
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

A Multimodal Approach to Heritage Preservation in the Context of Climate Change
por: Roqui, David, et al.
Publicado: (2025)

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
por: Li, Mengming, et al.
Publicado: (2026)

Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching
por: Chen, Zixiao, et al.
Publicado: (2024)

Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads
por: Khabbazan, Bahareh, et al.
Publicado: (2025)

ARAS: An Adaptive Low-Cost ReRAM-Based Accelerator for DNNs
por: Sabri, Mohammad, et al.
Publicado: (2024)

Hamun: An Approximate Computation Method to Prolong the Lifespan of ReRAM-Based Accelerators
por: Sabri, Mohammad, et al.
Publicado: (2025)

A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
por: Bonet, Marc Solé i, et al.
Publicado: (2025)

Using a Performance Model to Implement a Superscalar CVA6
por: Allart, Côme, et al.
Publicado: (2024)

Scalable data concentrator with baseline interconnection network for triggerless data acquisition systems
por: Zabołotny, Wojciech M.
Publicado: (2023)

LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation
por: Riedel, Samuel, et al.
Publicado: (2024)

Wildcat: Educational RISC-V Microprocessors
por: Schoeberl, Martin
Publicado: (2025)

CIMple: Standard-cell SRAM-based CIM with LUT-based split softmax for attention acceleration
por: Ahn, Bas, et al.
Publicado: (2026)

Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells
por: Van Brandt, Léopold, et al.
Publicado: (2024)

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
por: Böttcher, Andreas, et al.
Publicado: (2024)

Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators
por: Mecik, Michael, et al.
Publicado: (2025)

Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
por: Böttcher, Andreas, et al.
Publicado: (2024)

A modular architecture for IMU-based data gloves
por: Carfì, Alessandro, et al.
Publicado: (2024)

The xPU-athalon: Quantifying the Competition of AI Acceleration
por: Golden, Alicia, et al.
Publicado: (2026)

Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap
por: Langhammer, Martin, et al.
Publicado: (2024)

Banked Memories for Soft SIMT Processors
por: Langhammer, Martin, et al.
Publicado: (2025)

A Statically and Dynamically Scalable Soft GPGPU
por: Langhammer, Martin, et al.
Publicado: (2024)

Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview
por: Aliyev, Ilkin, et al.
Publicado: (2024)

A 950 MHz SIMT Soft Processor
por: Langhammer, Martin, et al.
Publicado: (2025)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
por: Tedeschi, Riccardo, et al.
Publicado: (2025)

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
por: Qin, Kun, et al.
Publicado: (2025)

A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
por: Raman, Siddhartha Raman Sundara, et al.
Publicado: (2026)

ACiS: Complex Processing in the Switch Fabric
por: Haghi, Pouya, et al.
Publicado: (2025)

Green Adaptation of Real-Time Web Services for Industrial CPS within a Cloud Environment
por: Higuera, Teresa, et al.
Publicado: (2024)

Thermal-Aware Floorplanner for 3D IC, including TSVs, Liquid Microchannels and Thermal Domains Optimization
por: Cuesta, David, et al.
Publicado: (2024)

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
por: Sauter, Philippe, et al.
Publicado: (2025)

StruM: Structured Mixed Precision for Efficient Deep Learning Hardware Codesign
por: Wu, Michael, et al.
Publicado: (2025)

A methodology to automatically optimize dynamic memory managers applying grammatical evolution
por: Risco-Martín, José L., et al.
Publicado: (2024)

Real Time Evolvable Hardware for Optimal Reconfiguration of Cusp-Like Pulse Shapers
por: Lanchares, Juan, et al.
Publicado: (2024)

Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration
por: Numan, Omar, et al.
Publicado: (2025)

Enhancing Instruction Prefetching via Cache and TLB Management
por: Jamet, Alexandre Valentin, et al.
Publicado: (2026)

Membrane: Accelerating Database Analytics with Bank-Level DRAM-PIM Filtering
por: Shekar, Akhil, et al.
Publicado: (2025)

RRAM-Based Bio-Inspired Circuits for Mobile Epileptic Correlation Extraction and Seizure Prediction
por: Wang, Hao, et al.
Publicado: (2024)

Characterizing the impact of last-level cache replacement policies on big-data workloads
por: Jamet, Alexandre Valentin, et al.
Publicado: (2023)

RISC-V Word-Size Modular Instructions for Residue Number Systems
por: Didier, Laurent-Stéphane, et al.
Publicado: (2024)

How to Increase Energy Efficiency with a Single Linux Command
por: Jelvani, Alborz, et al.
Publicado: (2025)