Cement2: Temporal Hardware Transactions for High-Level and Efficient FPGA Programming
Fuente:
arXiv
Saved in:
| Main Authors: | Xiao, Youwei, Luo, Zizhang, Peng, Weijie, Zou, Yuyang, Liang, Yun |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
SkyEgg: Joint Implementation Selection and Scheduling for Hardware Synthesis using E-graphs
by: Xiao, Youwei, et al.
Published: (2025)
by: Xiao, Youwei, et al.
Published: (2025)
LLM-Guided Strategy Synthesis for Scalable Equality Saturation
by: Yin, Chenyun, et al.
Published: (2026)
by: Yin, Chenyun, et al.
Published: (2026)
Using Read Promotion and Mixed Isolation Levels for Performant Yet Serializable Execution of Transaction Programs
by: Vandevoort, Brecht, et al.
Published: (2025)
by: Vandevoort, Brecht, et al.
Published: (2025)
On the Complexity of Checking Mixed Isolation Levels for SQL Transactions
by: Bouajjani, Ahmed, et al.
Published: (2025)
by: Bouajjani, Ahmed, et al.
Published: (2025)
Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
by: Tanaka, Izumi, et al.
Published: (2026)
by: Tanaka, Izumi, et al.
Published: (2026)
MHRC-Bench: A Multilingual Hardware Repository-Level Code Completion benchmark
by: Zou, Qingyun, et al.
Published: (2026)
by: Zou, Qingyun, et al.
Published: (2026)
Programming with High-Level Abstractions, Proceedings of the 3rd Workshop on Logic and Practice of Programming
by: Warren, David S., et al.
Published: (2024)
by: Warren, David S., et al.
Published: (2024)
FPGA Technology Mapping Using Sketch-Guided Program Synthesis
by: Smith, Gus Henry, et al.
Published: (2024)
by: Smith, Gus Henry, et al.
Published: (2024)
Hive: A Multi-Agent Infrastructure for Algorithm- and Task-Level Scaling
by: Luo, Zizhang, et al.
Published: (2026)
by: Luo, Zizhang, et al.
Published: (2026)
Qutes: A High-Level Quantum Programming Language for Simplified Quantum Computing
by: Faro, Simone, et al.
Published: (2025)
by: Faro, Simone, et al.
Published: (2025)
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
by: Zhang, Weichuang, et al.
Published: (2024)
by: Zhang, Weichuang, et al.
Published: (2024)
Automated Auxiliary Qubit Allocation in High-Level Quantum Programming
by: Rosa, Evandro C. R., et al.
Published: (2024)
by: Rosa, Evandro C. R., et al.
Published: (2024)
QPanda3: A High-Performance Software-Hardware Collaborative Framework for Large-Scale Quantum-Classical Computing Integration
by: Zou, Tianrui, et al.
Published: (2025)
by: Zou, Tianrui, et al.
Published: (2025)
Theorem-Carrying Transactions: Runtime Verification to Ensure Interface Specifications for Smart Contract Safety
by: Ball, Thomas, et al.
Published: (2024)
by: Ball, Thomas, et al.
Published: (2024)
Abstract Interpretation of Temporal Safety Effects of Higher Order Programs
by: Nicola, Mihai, et al.
Published: (2024)
by: Nicola, Mihai, et al.
Published: (2024)
Toward Verified Library-Level Choreographic Programming with Algebraic Effects
by: Shen, Gan, et al.
Published: (2024)
by: Shen, Gan, et al.
Published: (2024)
Qrisp: A Framework for Compilable High-Level Programming of Gate-Based Quantum Computers
by: Seidel, Raphael, et al.
Published: (2024)
by: Seidel, Raphael, et al.
Published: (2024)
Very High Level Programming Languages (e.g., SNOBOL, COMIT) in the Special Librarian's Future
by: Libbey, Miles A.
Published: (1975)
by: Libbey, Miles A.
Published: (1975)
Efficient, Portable, Census-Polymorphic Choreographic Programming
by: Bates, Mako, et al.
Published: (2024)
by: Bates, Mako, et al.
Published: (2024)
A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation
by: Lei, Jie, et al.
Published: (2025)
by: Lei, Jie, et al.
Published: (2025)
Wavefront Threading Enables Effective High-Level Synthesis
by: Pelton, Blake, et al.
Published: (2024)
by: Pelton, Blake, et al.
Published: (2024)
Dataflow-Based Optimization for Quantum Intermediate Representation Programs
by: Luo, Junjie, et al.
Published: (2024)
by: Luo, Junjie, et al.
Published: (2024)
\texttt{ReMind}: Understanding Deductive Code Reasoning in LLMs
by: Gao, Jun, et al.
Published: (2025)
by: Gao, Jun, et al.
Published: (2025)
Vbox: Efficient Black-Box Serializability Verification
by: Sun, Weihua, et al.
Published: (2025)
by: Sun, Weihua, et al.
Published: (2025)
Cage: Hardware-Accelerated Safe WebAssembly
by: Fink, Martin, et al.
Published: (2024)
by: Fink, Martin, et al.
Published: (2024)
DRReduce: Enhancing Syntax-Guided Program Reduction with Dependency Reconstruction
by: Feng, Qiong, et al.
Published: (2026)
by: Feng, Qiong, et al.
Published: (2026)
Structural Temporal Logic for Mechanized Program Verification
by: Ioannidis, Eleftherios, et al.
Published: (2024)
by: Ioannidis, Eleftherios, et al.
Published: (2024)
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design
by: Meech, James T.
Published: (2023)
by: Meech, James T.
Published: (2023)
Expression Acceleration: Seamless Parallelization of Typed High-Level Languages
by: Hummelgren, Lars, et al.
Published: (2022)
by: Hummelgren, Lars, et al.
Published: (2022)
vLLM Hook v0: A Plug-in for Programming Model Internals on vLLM
by: Ko, Ching-Yun, et al.
Published: (2026)
by: Ko, Ching-Yun, et al.
Published: (2026)
Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design
by: DeLorenzo, Matthew, et al.
Published: (2025)
by: DeLorenzo, Matthew, et al.
Published: (2025)
Tilus: A Tile-Level GPGPU Programming Language for Low-Precision Computation
by: Ding, Yaoyao, et al.
Published: (2025)
by: Ding, Yaoyao, et al.
Published: (2025)
Context-Free Grammar Inference for Complex Programming Languages in Black Box Settings
by: Li, Feifei, et al.
Published: (2026)
by: Li, Feifei, et al.
Published: (2026)
Register Aggregation for Hardware Decompilation
by: Rao, Varun, et al.
Published: (2024)
by: Rao, Varun, et al.
Published: (2024)
Interaction Tree Semantics for RISC-V: Bridging Compiler and Hardware Verification
by: Kan, Shuanglong, et al.
Published: (2026)
by: Kan, Shuanglong, et al.
Published: (2026)
Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design
by: Zhao, Shuqing
Published: (2026)
by: Zhao, Shuqing
Published: (2026)
DITRON: Distributed Multi-level Tiling Compiler for Parallel Tensor Programs
by: Zheng, Size, et al.
Published: (2026)
by: Zheng, Size, et al.
Published: (2026)
Qmod: Expressive High-Level Quantum Modeling
by: Vax, Matan, et al.
Published: (2025)
by: Vax, Matan, et al.
Published: (2025)
LightMamba: Efficient Mamba Acceleration on FPGA with Quantization and Hardware Co-design
by: Wei, Renjie, et al.
Published: (2025)
by: Wei, Renjie, et al.
Published: (2025)
SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
by: Khan, M Zafir Sadik, et al.
Published: (2025)
by: Khan, M Zafir Sadik, et al.
Published: (2025)
Similar Items
-
SkyEgg: Joint Implementation Selection and Scheduling for Hardware Synthesis using E-graphs
by: Xiao, Youwei, et al.
Published: (2025) -
LLM-Guided Strategy Synthesis for Scalable Equality Saturation
by: Yin, Chenyun, et al.
Published: (2026) -
Using Read Promotion and Mixed Isolation Levels for Performant Yet Serializable Execution of Transaction Programs
by: Vandevoort, Brecht, et al.
Published: (2025) -
On the Complexity of Checking Mixed Isolation Levels for SQL Transactions
by: Bouajjani, Ahmed, et al.
Published: (2025) -
Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
by: Tanaka, Izumi, et al.
Published: (2026)