Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators
Fuente:
arXiv
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| Main Authors: | Zhang, Jinsong, Li, Minghe, Tian, Jiayi, Lu, Jinming, Zhang, Zheng |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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