QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design

Fuente: arXiv
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Main Authors: Huang, Lei, Zhang, Rui, Guo, Jiaming, Zhang, Yang, Huang, Di, Cheng, Shuyao, Jin, Pengwei, Li, Chongxiao, Du, Zidong, Hu, Xing, Chen, Yunji, Guo, Qi
Format: Preprint
Published: 2025
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_version_ 1866915829607563264
author Huang, Lei
Zhang, Rui
Guo, Jiaming
Zhang, Yang
Huang, Di
Cheng, Shuyao
Jin, Pengwei
Li, Chongxiao
Du, Zidong
Hu, Xing
Chen, Yunji
Guo, Qi
author_facet Huang, Lei
Zhang, Rui
Guo, Jiaming
Zhang, Yang
Huang, Di
Cheng, Shuyao
Jin, Pengwei
Li, Chongxiao
Du, Zidong
Hu, Xing
Chen, Yunji
Guo, Qi
contents Large language models (LLMs) have shown promising capabilities in hardware description language (HDL) generation. However, existing approaches often rely on free-form natural language descriptions that are often ambiguous, redundant, and unstructured, which poses significant challenges for downstream Verilog code generation. We treat hardware code generation as a complex transformation from an open-ended natural language space to a domain-specific, highly constrained target space. To bridge this gap, we introduce Core Refined Understanding eXpression (CRUX), a structured intermediate space that captures the essential semantics of user intent while organizing the expression for precise Verilog code generation. We further design a two-stage training framework, comprising Joint Expression Modeling and Dual-Space Optimization, to enhance the quality of both CRUX and Verilog code. Experiments across multiple Verilog generation benchmarks demonstrate that our model, CRUX-V, achieves state-of-the-art performance among general models, particularly under challenging design tasks. Furthermore, the CRUX space proves transferable and beneficial when used as input prompts for other code models, highlighting its effectiveness in narrowing the gap between free-form natural language descriptions and precise Verilog generation.
format Preprint
id arxiv_https___arxiv_org_abs_2511_20099
institution arXiv
publishDate 2025
record_format arxiv
spellingShingle QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design
Huang, Lei
Zhang, Rui
Guo, Jiaming
Zhang, Yang
Huang, Di
Cheng, Shuyao
Jin, Pengwei
Li, Chongxiao
Du, Zidong
Hu, Xing
Chen, Yunji
Guo, Qi
Machine Learning
Hardware Architecture
Programming Languages
Large language models (LLMs) have shown promising capabilities in hardware description language (HDL) generation. However, existing approaches often rely on free-form natural language descriptions that are often ambiguous, redundant, and unstructured, which poses significant challenges for downstream Verilog code generation. We treat hardware code generation as a complex transformation from an open-ended natural language space to a domain-specific, highly constrained target space. To bridge this gap, we introduce Core Refined Understanding eXpression (CRUX), a structured intermediate space that captures the essential semantics of user intent while organizing the expression for precise Verilog code generation. We further design a two-stage training framework, comprising Joint Expression Modeling and Dual-Space Optimization, to enhance the quality of both CRUX and Verilog code. Experiments across multiple Verilog generation benchmarks demonstrate that our model, CRUX-V, achieves state-of-the-art performance among general models, particularly under challenging design tasks. Furthermore, the CRUX space proves transferable and beneficial when used as input prompts for other code models, highlighting its effectiveness in narrowing the gap between free-form natural language descriptions and precise Verilog generation.
title QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design
topic Machine Learning
Hardware Architecture
Programming Languages
url https://arxiv.org/abs/2511.20099