A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Arquint, Flurin, Castañeda, Oscar, Marti, Gian, Studer, Christoph
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Internet

https://arxiv.org/abs/2511.21451