A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm
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arXiv
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| Hauptverfasser: | , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2025
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| _version_ | 1866915639282630656 |
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| author | Arquint, Flurin Castañeda, Oscar Marti, Gian Studer, Christoph |
| author_facet | Arquint, Flurin Castañeda, Oscar Marti, Gian Studer, Christoph |
| contents | We present the first ASIC implementation of jammer-resilient multi-antenna time synchronization. The ASIC implements a recent algorithm that mitigates jamming attacks on synchronization signals using multi-antenna processing. Our design supports synchronization between a single-antenna transmitter and a 16-antenna receiver while mitigating smart jammers with up to two transmit antennas. The fabricated 65 nm ASIC has a core area of 2.87 mm$^2$, consumes a power of 310 mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s). |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_21451 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm Arquint, Flurin Castañeda, Oscar Marti, Gian Studer, Christoph Hardware Architecture We present the first ASIC implementation of jammer-resilient multi-antenna time synchronization. The ASIC implements a recent algorithm that mitigates jamming attacks on synchronization signals using multi-antenna processing. Our design supports synchronization between a single-antenna transmitter and a 16-antenna receiver while mitigating smart jammers with up to two transmit antennas. The fabricated 65 nm ASIC has a core area of 2.87 mm$^2$, consumes a power of 310 mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s). |
| title | A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2511.21451 |