Cover Image

A 0.32 mm$^2$ 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Elmiger, Jonas, Stuber, Fabian, Castañeda, Oscar, Marti, Gian, Studer, Christoph
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Signal Processing
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

A Jammer-Mitigating 267 Mb/s 3.78 mm$^2$ 583 mW 32$\times$8 Multi-User MIMO Receiver in 22FDX
by: Bucheli, Florian, et al.
Published: (2024)

A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm
by: Arquint, Flurin, et al.
Published: (2025)

A 1.2 mm$^2$ 416 mW 1.44 Mmat/s 64$\times$16 Matrix Preprocessing ASIC for Massive MIMO in 22FDX
by: Nonaca, Darja, et al.
Published: (2024)

GNSS Jammer and Spoofer Mitigation via Multi-Antenna Processing
by: Elmiger, Jonas, et al.
Published: (2025)

A 14ns-Latency 9Gb/s 0.44mm$^2$ 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
by: Nonaca, Darja, et al.
Published: (2025)

A 46 Gbps 12 pJ/b Sparsity-Adaptive Beamspace Equalizer for mmWave Massive MIMO in 22FDX
by: Mirfarshbafan, Seyed Hadi, et al.
Published: (2024)

Joint Jammer Mitigation and Data Detection
by: Marti, Gian, et al.
Published: (2025)

Universal MIMO Jammer Mitigation
by: Marti, Gian, et al.
Published: (2024)

A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations
by: Konno, Shota, et al.
Published: (2025)

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
by: Yu, Cunxi
Published: (2025)

Beamspace Equalization for mmWave Massive MIMO: Algorithms and VLSI Implementations
by: Mirfarshbafan, Seyed Hadi, et al.
Published: (2025)

AiEDA: Agentic AI Design Framework for Digital ASIC System Design
by: Patra, Aditya, et al.
Published: (2024)

BioTrain: Sub-MB, Sub-50mW On-Device Fine-Tuning for Edge-AI on Biosignals
by: Wang, Run, et al.
Published: (2026)

Jammer-Resilient Time Synchronization in the MIMO Uplink
by: Marti, Gian, et al.
Published: (2024)

Variable Point: A Number Format for Area- and Energy-Efficient Multiplication of High-Dynamic-Range Numbers
by: Mirfarshbafan, Seyed Hadi, et al.
Published: (2025)

Practical Timing Closure in FPGA and ASIC Designs: Methods, Challenges, and Case Studies
by: Darvishi, Mostafa
Published: (2025)

An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems
by: Gonul, Yilmaz Ege, et al.
Published: (2026)

ASIC-based Compression Accelerators for Storage Systems: Design, Placement, and Profiling Insights
by: Lu, Tao, et al.
Published: (2025)

Digital ASIC Design with Ongoing LLMs: Strategies and Prospects
by: Xiang, Maoyang, et al.
Published: (2024)

Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
by: Armato, Antonino, et al.
Published: (2026)

From LLM to Silicon: RL-Driven ASIC Architecture Exploration for On-Device AI Inference
by: Ganti, Ravindra, et al.
Published: (2026)

From English to ASIC: Hardware Implementation with Large Language Model
by: Goh, Emil, et al.
Published: (2024)

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
by: Darvishi, Mostafa
Published: (2025)

MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning
by: Liu, Mingju, et al.
Published: (2024)

Fundamental Limits for Jammer-Resilient Communication in Finite-Resolution MIMO
by: Marti, Gian, et al.
Published: (2024)

Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
by: Bostancı, F. Nisa, et al.
Published: (2025)

Leveraging ASIC AI Chips for Homomorphic Encryption
by: Tong, Jianming, et al.
Published: (2025)

ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation
by: Allam, Ahmed, et al.
Published: (2025)

Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation
by: Ke, Chih-Hua
Published: (2026)

A 28 nm AI microcontroller with tightly coupled zero-standby power weight memory featuring standard logic compatible 4 Mb 4-bits/cell embedded flash technology
by: Kim, Daewung, et al.
Published: (2025)

Fixed-Throughput GRAND with FIFO Scheduling
by: Christen, Filippo, et al.
Published: (2025)

Efficient Implementation of CRYSTALS-KYBER Key Encapsulation Mechanism on ESP32
by: Segatz, Fabian, et al.
Published: (2025)

Channel-Coherence-Adaptive Two-Stage Fully Digital Combining for mmWave MIMO Systems
by: Khorsandmanesh, Yasaman, et al.
Published: (2025)

Low-Complexity Beamspace Channel Denoiser for mmWave Massive MIMO with Low-Resolution ADCs
by: Park, Hanyoung, et al.
Published: (2026)

A Compact, Low Power Transprecision ALU for Smart Edge Devices
by: Dube, Ayushi, et al.
Published: (2025)

Improving Chip Design Enablement for Universities in Europe -- A Position Paper
by: Krupp, Lukas, et al.
Published: (2025)

A 0.5V, 6.2$μ$W, 0.059mm$^{2}$ Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing
by: Kim, Kwantae, et al.
Published: (2024)

Spectral Impact of Mismatches in Interleaved ADCs
by: Guichemerre, Jérémy, et al.
Published: (2026)

Sequence-Aware Split Heuristic to Mitigate SM Underutilization in FlashAttention-3 Low-Head-Count Decoding
by: Font, Martí Llopart, et al.
Published: (2026)

A 0.03${mm}^2$ 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing
by: Ray, Yudhajit, et al.
Published: (2024)