FPGA-Enabled Modulo ADC with x100 Dynamic-Range Expansion: Hardware Design and Performance Evaluation
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arXiv
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| Autori principali: | , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866917110918152192 |
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| author | Li, Zeyuan Yan, Wenyi Gan, Lu Li, Guoquan Liu, Hongqing |
| author_facet | Li, Zeyuan Yan, Wenyi Gan, Lu Li, Guoquan Liu, Hongqing |
| contents | Conventional analog-to-digital converters (ADCs) fail to capture high-dynamic-range (HDR) signals due to clipping. Modulo ADCs circumvent this limitation by folding the input prior to quantization and algorithmically reconstructing the original waveform. This work presents a field-programmable gate array (FPGA)-based modulo ADC platform for systematic HDR performance evaluation. The mixed-signal architecture integrates a precision analog front end with a 200-MHz FPGA control loop that incorporates multi-bit updates and digital under-compensation calibration, ensuring stable folding and accurate feedback generation. The system achieves more than a hundred-fold dynamic-range expansion within a 400-kHz bandwidth while maintaining fidelity comparable to that of a conventional ADC. A system-on-chip (SoC)-like implementation enables on-board real-time recovery and supports benchmarking of state-of-the-art reconstruction algorithms, providing a compact and practical framework for HDR signal acquisition and evaluation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_22752 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | FPGA-Enabled Modulo ADC with x100 Dynamic-Range Expansion: Hardware Design and Performance Evaluation Li, Zeyuan Yan, Wenyi Gan, Lu Li, Guoquan Liu, Hongqing Signal Processing Conventional analog-to-digital converters (ADCs) fail to capture high-dynamic-range (HDR) signals due to clipping. Modulo ADCs circumvent this limitation by folding the input prior to quantization and algorithmically reconstructing the original waveform. This work presents a field-programmable gate array (FPGA)-based modulo ADC platform for systematic HDR performance evaluation. The mixed-signal architecture integrates a precision analog front end with a 200-MHz FPGA control loop that incorporates multi-bit updates and digital under-compensation calibration, ensuring stable folding and accurate feedback generation. The system achieves more than a hundred-fold dynamic-range expansion within a 400-kHz bandwidth while maintaining fidelity comparable to that of a conventional ADC. A system-on-chip (SoC)-like implementation enables on-board real-time recovery and supports benchmarking of state-of-the-art reconstruction algorithms, providing a compact and practical framework for HDR signal acquisition and evaluation. |
| title | FPGA-Enabled Modulo ADC with x100 Dynamic-Range Expansion: Hardware Design and Performance Evaluation |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2511.22752 |