Cover Image

Analysis of Single Event Induced Bit Faults in a Deep Neural Network Accelerator Pipeline

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Jonckers, Naïn, Vinck, Toon, Karsmakers, Peter, Prinzie, Jeffrey
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Single-Event Upset Analysis of a Systolic Array based Deep Neural Network Accelerator
by: Jonckers, Naïn, et al.
Published: (2024)

Mitigating multiple single-event upsets during deep neural network inference using fault-aware training
by: Vinck, Toon, et al.
Published: (2025)

Monitor Placement for Fault Localization in Deep Neural Network Accelerators
by: Liu, Wei-Kai
Published: (2023)

Bit-Flip Fault Attack: Crushing Graph Neural Networks via Gradual Bit Search
by: Abharian, Sanaz Kazemi, et al.
Published: (2025)

BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Acceleration
by: Rakka, Mariam, et al.
Published: (2024)

Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs
by: Souvatzoglou, Ioanna, et al.
Published: (2024)

RAS: A Bit-Exact rANS Accelerator For High-Performance Neural Lossless Compression
by: Qin, Yuchao, et al.
Published: (2025)

Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults
by: Alama, Youssef A. Ait, et al.
Published: (2024)

In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
by: Spagnolo, Tommaso, et al.
Published: (2026)

Edge GPU Aware Multiple AI Model Pipeline for Accelerated MRI Reconstruction and Analysis
by: Majeed, Ashiyana Abdul, et al.
Published: (2025)

High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator
by: Lin, Kuan-Ting, et al.
Published: (2025)

Special Session: Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators
by: Qin, Yifan, et al.
Published: (2025)

BBS: Bi-directional Bit-level Sparsity for Deep Learning Acceleration
by: Chen, Yuzong, et al.
Published: (2024)

SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators
by: Umuroglu, Yaman, et al.
Published: (2025)

Oobleck: Low-Compromise Design for Fault Tolerant Accelerators
by: Wilks, Guy, et al.
Published: (2025)

Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework
by: Malhotra, Akul, et al.
Published: (2025)

AccelSync: Verifying Synchronization Coverage in Accelerator Pipeline Programs
by: An, Hangcheng, et al.
Published: (2026)

Bit Transition Reduction by Data Transmission Ordering in NoC-based DNN Accelerator
by: Chen, Yizhi, et al.
Published: (2025)

BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration
by: Chen, Yuzong, et al.
Published: (2024)

Switchable Single/Dual Edge Registers for Pipeline Architecture
by: Singh, Suyash Vardhan, et al.
Published: (2024)

A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks
by: Yi, Zhiqiang, et al.
Published: (2025)

Platinum: Path-Adaptable LUT-Based Accelerator Tailored for Low-Bit Weight Matrix Multiplication
by: Shan, Haoxuan, et al.
Published: (2025)

Prosperity: Accelerating Spiking Neural Networks via Product Sparsity
by: Wei, Chiyue, et al.
Published: (2025)

Architecture-Level Modeling of Photonic Deep Neural Network Accelerators
by: Andrulis, Tanner, et al.
Published: (2024)

Honest to a Fault: Root-Causing Fault Attacks with Pre-Silicon RISC Pipeline Characterization
by: Malik, Arsalan Ali, et al.
Published: (2025)

High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic
by: Alexakis, George, et al.
Published: (2025)

DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network
by: Ahmadilivani, Mohammad Hasan, et al.
Published: (2024)

FsimNNs: An Open-Source Graph Neural Network Platform for SEU Simulation-based Fault Injection
by: Lu, Li, et al.
Published: (2025)

FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training
by: Lu, Jinming, et al.
Published: (2025)

MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness
by: Wang, Huizheng, et al.
Published: (2025)

Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators
by: Huang, Zongle, et al.
Published: (2026)

PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance
by: Ji, Shixin, et al.
Published: (2026)

Approximate Multiplier Induced Error Propagation in Deep Neural Networks
by: Alahakoon, A. M. H. H., et al.
Published: (2025)

Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators
by: Masar, Filip, et al.
Published: (2025)

Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space
by: Leon, Vasileios, et al.
Published: (2025)

CIMPool: Scalable Neural Network Acceleration for Compute-In-Memory using Weight Pools
by: Li, Shurui, et al.
Published: (2025)

A Bit Level Weight Reordering Strategy Based on Column Similarity to Explore Weight Sparsity in RRAM-based NN Accelerator
by: Yang, Weiping, et al.
Published: (2025)

Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators
by: Klhufek, Jan, et al.
Published: (2024)

Generalized Ping-Pong: Off-Chip Memory Bandwidth Centric Pipelining Strategy for Processing-In-Memory Accelerators
by: Wang, Ruibao, et al.
Published: (2024)

MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications
by: Abdollahi, Armin, et al.
Published: (2024)