A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions
Fuente:
arXiv
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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2025
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| _version_ | 1866915644993175552 |
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| author | M, Amogh K S, Sunita M |
| author_facet | M, Amogh K S, Sunita M |
| contents | This paper presents an in-memory computing (IMC) architecture developed on an 8x8 array of 8T SRAM cells. This architecture enables both multi-bit parallel Multiply-Accumulate (MAC) operations and standard memory processing through charge-sharing on dedicated read bit-lines. By leveraging the maturity of SRAM technology, this work introduces an 8T SRAM-based IMC architecture that decouples read and write paths, thereby overcoming the reliability limitations of prior 6T SRAM designs. A novel analog-to-digital decoding scheme converts the MAC voltage output into digital counts, which are subsequently interpreted to realize fundamental logic functions including AND/NAND, NOR/OR, XOR/XNOR, and 1-bit addition within the same array. Simulated in a 90 nm CMOS process at 1.8 V supply voltage, the proposed design achieves 8-bit MAC and logical operations at a frequency of 142.85 MHz, with a latency of 0.7 ns and energy consumption of 56.56 fJ/bit per MAC operation and throughput of 15.8 M operations/s. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_00441 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions M, Amogh K S, Sunita M Hardware Architecture Emerging Technologies This paper presents an in-memory computing (IMC) architecture developed on an 8x8 array of 8T SRAM cells. This architecture enables both multi-bit parallel Multiply-Accumulate (MAC) operations and standard memory processing through charge-sharing on dedicated read bit-lines. By leveraging the maturity of SRAM technology, this work introduces an 8T SRAM-based IMC architecture that decouples read and write paths, thereby overcoming the reliability limitations of prior 6T SRAM designs. A novel analog-to-digital decoding scheme converts the MAC voltage output into digital counts, which are subsequently interpreted to realize fundamental logic functions including AND/NAND, NOR/OR, XOR/XNOR, and 1-bit addition within the same array. Simulated in a 90 nm CMOS process at 1.8 V supply voltage, the proposed design achieves 8-bit MAC and logical operations at a frequency of 142.85 MHz, with a latency of 0.7 ns and energy consumption of 56.56 fJ/bit per MAC operation and throughput of 15.8 M operations/s. |
| title | A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions |
| topic | Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2512.00441 |