A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions

Documenti analoghi

• A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells
  di: Dizabadi, Naser Khatti, et al.
  Pubblicazione: (2026)
• Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM
  di: Hajisadeghi, Amir M., et al.
  Pubblicazione: (2024)
• PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro with In-Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout
  di: Chen, Zhiyu, et al.
  Pubblicazione: (2024)
• Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)
  di: Challagundla, Dhandeep, et al.
  Pubblicazione: (2024)
• Modeling and Simulation Frameworks for Processing-in-Memory Architectures
  di: Aghaei, Mahdi, et al.
  Pubblicazione: (2025)