Partial Cross-Compilation and Mixed Execution for Accelerating Dynamic Binary Translation
Fuente:
arXiv
Guardado en:
| Autores principales: | Gu, Yuhao, Zheng, Zhongchun, Xiao, Nong, Lu, Yutong, Zhang, Xianwei |
|---|---|
| Formato: | Preprint |
| Publicado: |
2025
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
ACT: Automatically Generating Compiler Backends from Tensor Accelerator ISA Descriptions
por: Jain, Devansh, et al.
Publicado: (2025)
por: Jain, Devansh, et al.
Publicado: (2025)
Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution
por: Rudkowski, Karl Aaron, et al.
Publicado: (2025)
por: Rudkowski, Karl Aaron, et al.
Publicado: (2025)
LLM-Aided Compilation for Tensor Accelerators
por: Hong, Charles, et al.
Publicado: (2024)
por: Hong, Charles, et al.
Publicado: (2024)
Understanding Accelerator Compilers via Performance Profiling
por: Yorihiro, Ayaka, et al.
Publicado: (2025)
por: Yorihiro, Ayaka, et al.
Publicado: (2025)
Generation of Compiler Backends from Formal Models of Hardware
por: Smith, Gus Henry
Publicado: (2024)
por: Smith, Gus Henry
Publicado: (2024)
NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures
por: Li, Shangkun, et al.
Publicado: (2026)
por: Li, Shangkun, et al.
Publicado: (2026)
WaveCert: Translation Validation for Asynchronous Dataflow Programs via Dynamic Fractional Permissions
por: Lin, Zhengyao, et al.
Publicado: (2023)
por: Lin, Zhengyao, et al.
Publicado: (2023)
The Program Hypergraph: Multi-Way Relational Structure for Geometric Algebra, Spatial Compute, and Physics-Aware Compilation
por: Haynes, Houston
Publicado: (2026)
por: Haynes, Houston
Publicado: (2026)
Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
por: Xu, Siyi, et al.
Publicado: (2025)
por: Xu, Siyi, et al.
Publicado: (2025)
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
por: Zhang, Weichuang, et al.
Publicado: (2024)
por: Zhang, Weichuang, et al.
Publicado: (2024)
Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
por: Tanaka, Izumi, et al.
Publicado: (2026)
por: Tanaka, Izumi, et al.
Publicado: (2026)
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
por: Zhuang, Jinming, et al.
Publicado: (2024)
por: Zhuang, Jinming, et al.
Publicado: (2024)
MINISA: Minimal Instruction Set Architecture for Next-gen Reconfigurable Inference Accelerator
por: Tong, Jianming, et al.
Publicado: (2026)
por: Tong, Jianming, et al.
Publicado: (2026)
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
por: Liu, Shang, et al.
Publicado: (2023)
por: Liu, Shang, et al.
Publicado: (2023)
Genesis: A Compiler Framework for Hamiltonian Simulation on Hybrid CV-DV Quantum Computers
por: Chen, Zihan, et al.
Publicado: (2025)
por: Chen, Zihan, et al.
Publicado: (2025)
FuseFlow: A Fusion-Centric Compilation Framework for Sparse Deep Learning on Streaming Dataflow
por: Lacouture, Rubens, et al.
Publicado: (2025)
por: Lacouture, Rubens, et al.
Publicado: (2025)
Allo: A Programming Model for Composable Accelerator Design
por: Chen, Hongzheng, et al.
Publicado: (2024)
por: Chen, Hongzheng, et al.
Publicado: (2024)
Dato: A Task-Based Programming Model for Dataflow Accelerators
por: Fang, Shihan, et al.
Publicado: (2025)
por: Fang, Shihan, et al.
Publicado: (2025)
PHOENIX: Pauli-Based High-Level Optimization Engine for Instruction Execution on NISQ Devices
por: Yang, Zhaohui, et al.
Publicado: (2025)
por: Yang, Zhaohui, et al.
Publicado: (2025)
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
por: Chen, Chen, et al.
Publicado: (2024)
por: Chen, Chen, et al.
Publicado: (2024)
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
por: Zhao, Zhuorui, et al.
Publicado: (2025)
por: Zhao, Zhuorui, et al.
Publicado: (2025)
HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers
por: Yang, Yiyao, et al.
Publicado: (2025)
por: Yang, Yiyao, et al.
Publicado: (2025)
Sim-FA: A GPGPU Simulator Framework for Fine-Grained FlashAttention Pipeline Analysis
por: Zhou, Zhongchun, et al.
Publicado: (2026)
por: Zhou, Zhongchun, et al.
Publicado: (2026)
DCO: Dynamic Cache Orchestration for LLM Accelerators through Predictive Management
por: Zhou, Zhongchun, et al.
Publicado: (2025)
por: Zhou, Zhongchun, et al.
Publicado: (2025)
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
por: Niu, Juxin, et al.
Publicado: (2025)
por: Niu, Juxin, et al.
Publicado: (2025)
HEC: Equivalence Verification Checking for Code Transformation via Equality Saturation
por: Yin, Jiaqi, et al.
Publicado: (2025)
por: Yin, Jiaqi, et al.
Publicado: (2025)
Register Aggregation for Hardware Decompilation
por: Rao, Varun, et al.
Publicado: (2024)
por: Rao, Varun, et al.
Publicado: (2024)
Relaxed exception semantics for Arm-A (extended version)
por: Simner, Ben, et al.
Publicado: (2024)
por: Simner, Ben, et al.
Publicado: (2024)
There and Back Again: A Netlist's Tale with Much Egraphin'
por: Smith, Gus Henry, et al.
Publicado: (2024)
por: Smith, Gus Henry, et al.
Publicado: (2024)
Scaling Program Synthesis Based Technology Mapping with Equality Saturation
por: Smith, Gus Henry, et al.
Publicado: (2024)
por: Smith, Gus Henry, et al.
Publicado: (2024)
SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop
por: Chang, Fu-Chieh, et al.
Publicado: (2026)
por: Chang, Fu-Chieh, et al.
Publicado: (2026)
Tywaves: A Typed Waveform Viewer for Chisel
por: Meloni, Raffaele, et al.
Publicado: (2024)
por: Meloni, Raffaele, et al.
Publicado: (2024)
From CISC to RISC: language-model guided assembly transpilation
por: Heakl, Ahmed, et al.
Publicado: (2024)
por: Heakl, Ahmed, et al.
Publicado: (2024)
Parameterized Hardware Design with Latency-Abstract Interfaces
por: Nigam, Rachit, et al.
Publicado: (2024)
por: Nigam, Rachit, et al.
Publicado: (2024)
FPGA Technology Mapping Using Sketch-Guided Program Synthesis
por: Smith, Gus Henry, et al.
Publicado: (2024)
por: Smith, Gus Henry, et al.
Publicado: (2024)
Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models
por: Xu, Haocheng, et al.
Publicado: (2024)
por: Xu, Haocheng, et al.
Publicado: (2024)
AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning
por: Tan, Yan, et al.
Publicado: (2026)
por: Tan, Yan, et al.
Publicado: (2026)
Streaming Tensor Programs: A Streaming Abstraction for Dynamic Parallelism
por: Sohn, Gina, et al.
Publicado: (2025)
por: Sohn, Gina, et al.
Publicado: (2025)
A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation
por: Lei, Jie, et al.
Publicado: (2025)
por: Lei, Jie, et al.
Publicado: (2025)
Compilation and Execution of an Embeddable YOLO-NAS on the VTA
por: Faure-Gignoux, Anthony, et al.
Publicado: (2026)
por: Faure-Gignoux, Anthony, et al.
Publicado: (2026)
Ejemplares similares
-
ACT: Automatically Generating Compiler Backends from Tensor Accelerator ISA Descriptions
por: Jain, Devansh, et al.
Publicado: (2025) -
Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution
por: Rudkowski, Karl Aaron, et al.
Publicado: (2025) -
LLM-Aided Compilation for Tensor Accelerators
por: Hong, Charles, et al.
Publicado: (2024) -
Understanding Accelerator Compilers via Performance Profiling
por: Yorihiro, Ayaka, et al.
Publicado: (2025) -
Generation of Compiler Backends from Formal Models of Hardware
por: Smith, Gus Henry
Publicado: (2024)