The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates
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arXiv
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| Main Authors: | , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866908691134939136 |
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| author | Ilmberger, Joscha Schemmel, Johannes |
| author_facet | Ilmberger, Joscha Schemmel, Johannes |
| contents | The BrainScaleS-2 SoC integrates analog neuron and synapse circuits with digital periphery, including two CPUs with SIMD extensions. Each ASIC is connected to a Node-FPGA, providing experiment control and Ethernet connectivity. This work details the scaling of the compute substrate through FPGA-based interconnection via an additional Aggregator unit. The Aggregator provides up to 12 transceiver links to a backplane of Node-FPGAs, as well as 4 transceiver lanes for further extension. Two such interconnected backplanes are integrated into a standard 19in rack case with 4U height together with an Ethernet switch, system controller and power supplies. For all spike rates, chip-to-chip latencies -- consisting of four hops across three FPGAs -- below 1.3$μ$s are achieved within each backplane. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_03781 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates Ilmberger, Joscha Schemmel, Johannes Hardware Architecture The BrainScaleS-2 SoC integrates analog neuron and synapse circuits with digital periphery, including two CPUs with SIMD extensions. Each ASIC is connected to a Node-FPGA, providing experiment control and Ethernet connectivity. This work details the scaling of the compute substrate through FPGA-based interconnection via an additional Aggregator unit. The Aggregator provides up to 12 transceiver links to a backplane of Node-FPGAs, as well as 4 transceiver lanes for further extension. Two such interconnected backplanes are integrated into a standard 19in rack case with 4U height together with an Ethernet switch, system controller and power supplies. For all spike rates, chip-to-chip latencies -- consisting of four hops across three FPGAs -- below 1.3$μ$s are achieved within each backplane. |
| title | The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2512.03781 |