A Spatial Array for Spectrally Agile Wireless Processing
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866909995104206848 |
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| author | Rasteh, Ali Hennessee, Andrew Shivhare, Ishaan Garg, Siddharth Rangan, Sundeep Reagen, Brandon |
| author_facet | Rasteh, Ali Hennessee, Andrew Shivhare, Ishaan Garg, Siddharth Rangan, Sundeep Reagen, Brandon |
| contents | Massive MIMO is a cornerstone of next-generation wireless communication, offering significant gains in capacity, reliability, and energy efficiency. However, to meet emerging demands such as high-frequency operation, wide bandwidths, co-existence, integrated sensing, and resilience to dynamic interference, future systems must exhibit both scalability and spectral agility. These requirements place increasing pressure on the underlying processing hardware to be both efficient and reconfigurable. This paper proposes a custom-designed spatial array architecture that serves as a reconfigurable, general-purpose core optimized for a class of wireless kernels that commonly arise in diverse communications and sensing tasks. The proposed spatial array is evaluated against specialized cores for each kernel using High-Level Synthesis (HLS). Both the reconfigurable and specialized designs are synthesized in a 32 nm process to assess latency, throughput, area, and power in realistic processes. The results identify conditions under which general-purpose systolic architectures can approach the efficiency of specialized cores, thereby paving the way toward more scalable and agile systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_04182 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Spatial Array for Spectrally Agile Wireless Processing Rasteh, Ali Hennessee, Andrew Shivhare, Ishaan Garg, Siddharth Rangan, Sundeep Reagen, Brandon Signal Processing Hardware Architecture Massive MIMO is a cornerstone of next-generation wireless communication, offering significant gains in capacity, reliability, and energy efficiency. However, to meet emerging demands such as high-frequency operation, wide bandwidths, co-existence, integrated sensing, and resilience to dynamic interference, future systems must exhibit both scalability and spectral agility. These requirements place increasing pressure on the underlying processing hardware to be both efficient and reconfigurable. This paper proposes a custom-designed spatial array architecture that serves as a reconfigurable, general-purpose core optimized for a class of wireless kernels that commonly arise in diverse communications and sensing tasks. The proposed spatial array is evaluated against specialized cores for each kernel using High-Level Synthesis (HLS). Both the reconfigurable and specialized designs are synthesized in a 32 nm process to assess latency, throughput, area, and power in realistic processes. The results identify conditions under which general-purpose systolic architectures can approach the efficiency of specialized cores, thereby paving the way toward more scalable and agile systems. |
| title | A Spatial Array for Spectrally Agile Wireless Processing |
| topic | Signal Processing Hardware Architecture |
| url | https://arxiv.org/abs/2512.04182 |