When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation
Fuente:
arXiv
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| Main Authors: | Liang, Yiwen, Li, Qiufeng, Wang, Shikai, Cao, Weidong |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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