From PyTorch to Calyx: An Open-Source Compiler Toolchain for ML Accelerators
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arXiv
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866908695450877952 |
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| author | Xie, Jiahan Williams, Evan Sampson, Adrian |
| author_facet | Xie, Jiahan Williams, Evan Sampson, Adrian |
| contents | We present an end-to-end open-source compiler toolchain that targets synthesizable SystemVerilog from ML models written in PyTorch. Our toolchain leverages the accelerator design language Allo, the hardware intermediate representation (IR) Calyx, and the CIRCT project under LLVM. We also implement a set of compiler passes for memory partitioning, enabling effective parallelism in memory-intensive ML workloads. Experimental results demonstrate that our compiler can effectively generate optimized FPGA-implementable hardware designs that perform reasonably well against closed-source industry-grade tools such as Vitis HLS. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_06177 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | From PyTorch to Calyx: An Open-Source Compiler Toolchain for ML Accelerators Xie, Jiahan Williams, Evan Sampson, Adrian Hardware Architecture We present an end-to-end open-source compiler toolchain that targets synthesizable SystemVerilog from ML models written in PyTorch. Our toolchain leverages the accelerator design language Allo, the hardware intermediate representation (IR) Calyx, and the CIRCT project under LLVM. We also implement a set of compiler passes for memory partitioning, enabling effective parallelism in memory-intensive ML workloads. Experimental results demonstrate that our compiler can effectively generate optimized FPGA-implementable hardware designs that perform reasonably well against closed-source industry-grade tools such as Vitis HLS. |
| title | From PyTorch to Calyx: An Open-Source Compiler Toolchain for ML Accelerators |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2512.06177 |