SparsePixels: Efficient Convolution for Sparse Data on FPGAs
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866918248744747008 |
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| author | Tsoi, Ho Fung Rankin, Dylan Loncar, Vladimir Harris, Philip |
| author_facet | Tsoi, Ho Fung Rankin, Dylan Loncar, Vladimir Harris, Philip |
| contents | Inference of standard convolutional neural networks (CNNs) on FPGAs often incurs high latency and a long initiation interval due to the deep nested loops required to densely convolve every input pixel regardless of its feature value. However, input features can be spatially sparse in some image data, where semantic information may occupy only a small fraction of the pixels and most computation would be wasted on empty regions. In this work, we introduce SparsePixels, a framework that implements sparse convolution on FPGAs by selectively retaining and computing on a small subset of active pixels while ignoring the rest. We show that, for identifying neutrino interactions in naturally sparse LArTPC images with 4k pixels, a standard CNN with a compact size of 4k parameters incurs an inference latency of 48.665 $μ$s on an FPGA, whereas a sparse CNN of the same base architecture, computing on less than 1% of the input pixels, achieves a $\times 73$ speedup to 0.665 $μ$s with resource utilization well within on-chip budgets, trading only a small percent-level performance loss. This work aims to benefit future algorithm development for efficient data readout in modern experiments with latency requirements of microseconds or below. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_06208 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | SparsePixels: Efficient Convolution for Sparse Data on FPGAs Tsoi, Ho Fung Rankin, Dylan Loncar, Vladimir Harris, Philip Hardware Architecture Machine Learning High Energy Physics - Experiment Inference of standard convolutional neural networks (CNNs) on FPGAs often incurs high latency and a long initiation interval due to the deep nested loops required to densely convolve every input pixel regardless of its feature value. However, input features can be spatially sparse in some image data, where semantic information may occupy only a small fraction of the pixels and most computation would be wasted on empty regions. In this work, we introduce SparsePixels, a framework that implements sparse convolution on FPGAs by selectively retaining and computing on a small subset of active pixels while ignoring the rest. We show that, for identifying neutrino interactions in naturally sparse LArTPC images with 4k pixels, a standard CNN with a compact size of 4k parameters incurs an inference latency of 48.665 $μ$s on an FPGA, whereas a sparse CNN of the same base architecture, computing on less than 1% of the input pixels, achieves a $\times 73$ speedup to 0.665 $μ$s with resource utilization well within on-chip budgets, trading only a small percent-level performance loss. This work aims to benefit future algorithm development for efficient data readout in modern experiments with latency requirements of microseconds or below. |
| title | SparsePixels: Efficient Convolution for Sparse Data on FPGAs |
| topic | Hardware Architecture Machine Learning High Energy Physics - Experiment |
| url | https://arxiv.org/abs/2512.06208 |