APA (7th ed.) Citation

Singha, A., Sett, S., Watanabe, K., Taniguchi, T., Ghosh, A., & Debnath, R. (2025). Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics.

Chicago Style (17th ed.) Citation

Singha, Arup, Shaili Sett, Kenji Watanabe, Takashi Taniguchi, Arindam Ghosh, and Rahul Debnath. Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics. 2025.

MLA (9th ed.) Citation

Singha, Arup, et al. Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics. 2025.