Citazione Stile APA (7a Edizione)

Singha, A., Sett, S., Watanabe, K., Taniguchi, T., Ghosh, A., & Debnath, R. (2025). Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics.

Citazione stile Chigago Style (17a edizione)

Singha, Arup, Shaili Sett, Kenji Watanabe, Takashi Taniguchi, Arindam Ghosh, e Rahul Debnath. Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics. 2025.

Citatione MLA (9a ed.)

Singha, Arup, et al. Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics. 2025.