Image de couverture de livre

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections

Fuente: arXiv

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Harlikar, Pracheta, Badawy, Abdel-Hameed A., Date, Prasanna
Format:	Preprint
Publié:	2025
Sujets:	Hardware Architecture
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

iThermTroj: Exploiting Intermittent Thermal Trojans in Multi-Processor System-on-Chips
par: Elahi, Mehdi, et autres
Publié: (2025)

FAST-Prefill: FPGA Accelerated Sparse Attention for Long Context LLM Prefill
par: Jayanth, Rakshith, et autres
Publié: (2026)

Efficient and Accurate Graph Classification with Hyperdimensional Computing on FPGA
par: Arockiaraj, Jebacyril, et autres
Publié: (2025)

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
par: Zhong, Yang, et autres
Publié: (2025)

MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation
par: Elahi, Mehdi, et autres
Publié: (2024)

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
par: Qin, Kun, et autres
Publié: (2025)

Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications
par: Leon, Vasileios, et autres
Publié: (2025)

FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation
par: Meng, Chengzhen, et autres
Publié: (2025)

On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
par: Elahi, Mehdi, et autres
Publié: (2025)

SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
par: He, Zicheng, et autres
Publié: (2026)

Trojan Playground: A Reinforcement Learning Framework for Hardware Trojan Insertion and Detection
par: Sarihi, Amin, et autres
Publié: (2023)

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
par: Yu, Cunxi
Publié: (2025)

FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption
par: Xu, Zhihan, et autres
Publié: (2025)

The Seeker's Dilemma: Realistic Formulation and Benchmarking for Hardware Trojan Detection
par: Sarihi, Amin, et autres
Publié: (2024)

Hiding in Plain Sight: Reframing Hardware Trojan Benchmarking as a Hide&Seek Modification
par: Sarihi, Amin, et autres
Publié: (2024)

TrojanForge: Generating Adversarial Hardware Trojan Examples Using Reinforcement Learning
par: Sarihi, Amin, et autres
Publié: (2024)

NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors
par: Nair, Harideep, et autres
Publié: (2024)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
par: Ottaviano, Alessandro, et autres
Publié: (2023)

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
par: Darvishi, Mostafa
Publié: (2025)

Adaptive Prognostic Malfunction Based Processor for Autonomous Landing Guidance Assistance System Using FPGA
par: Ahmed, Hossam O., et autres
Publié: (2024)

Banked Memories for Soft SIMT Processors
par: Langhammer, Martin, et autres
Publié: (2025)

An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors
par: Su, Zhe, et autres
Publié: (2024)

Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
par: Pham, Anh Kiet, et autres
Publié: (2026)

A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
par: Gupta, Neelesh, et autres
Publié: (2026)

Large Processor Chip Model
par: Chang, Kaiyan, et autres
Publié: (2025)

A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing
par: Zhou, P. J., et autres
Publié: (2024)

SAMIPS: A Synthesised Asynchronous Processor
par: Zhang, Qianyi, et autres
Publié: (2024)

FPGA-based Hyrbid Memory Emulation System
par: Wen, Fei, et autres
Publié: (2020)

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
par: Barocci, Michelangelo, et autres
Publié: (2026)

From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors
par: Yousefzadeh, Amirreza
Publié: (2025)

Link Quality Aware Pathfinding for Chiplet Interconnects
par: Yen, Aaron, et autres
Publié: (2026)

A 950 MHz SIMT Soft Processor
par: Langhammer, Martin, et autres
Publié: (2025)

Hypervisor Extension for a RISC-V Processor
par: Gauchola, Jaume, et autres
Publié: (2024)

Holistic Optimization Framework for FPGA Accelerators
par: Pouget, Stéphane, et autres
Publié: (2025)

When Routers, Switches and Interconnects Compute: A processing-in-interconnect Paradigm for Scalable Neuromorphic AI
par: Srivatsav, Madhuvanthi, et autres
Publié: (2025)

Governance at the Edge of Architecture: Regulating NeuroAI and Neuromorphic Systems
par: Kashif, Afifah, et autres
Publié: (2026)

GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
par: Sudarshan, Chetan Choppali, et autres
Publié: (2023)

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
par: Iff, Patrick, et autres
Publié: (2025)

Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
par: Wang, Xiaoke, et autres
Publié: (2026)

Implementation of Compute Intensive Algorithms on Software Configurable Processor
par: Ganesha, et autres
Publié: (2025)