PD-Swap: Prefill-Decode Logic Swapping for End-to-End LLM Inference on Edge FPGAs via Dynamic Partial Reconfiguration
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arXiv
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| Main Authors: | Zhang, Yifan, Chen, Zhiheng, Qiao, Ye, Huang, Sitao |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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