Design in Tiles: Automating GEMM Deployment on Tile-Based Many-PE Accelerators
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866914202054033408 |
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| author | Shen, Aofeng Zhang, Chi Budanaz, Yakup Calotoiu, Alexandru Hoefler, Torsten Benini, Luca |
| author_facet | Shen, Aofeng Zhang, Chi Budanaz, Yakup Calotoiu, Alexandru Hoefler, Torsten Benini, Luca |
| contents | Tile-based many-Processing Element (PE) accelerators can achieve competitive performance on General Matrix Multiplication (GEMM), but they are extremely hard to program, as their optimal software mapping is deeply coupled with hardware design which is unwieldy to manual deployment. We propose "Design in Tiles (DiT)", an automated framework connecting a deployment toolchain with a configurable executable model for these accelerators. For evaluation, we apply our framework to GEMM targeting a large acceleration configuration (e.g., 32x32 tiles, 1979 TFLOPS@FP8, 4 TB/s Bandwidth) comparable to an NVIDIA GH200. We achieve higher PE utilization than GH200 with its expert-tuned GEMM libraries, achieving 1.2-2.0x speedup across diverse matrix shapes. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_13638 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Design in Tiles: Automating GEMM Deployment on Tile-Based Many-PE Accelerators Shen, Aofeng Zhang, Chi Budanaz, Yakup Calotoiu, Alexandru Hoefler, Torsten Benini, Luca Distributed, Parallel, and Cluster Computing Hardware Architecture Tile-based many-Processing Element (PE) accelerators can achieve competitive performance on General Matrix Multiplication (GEMM), but they are extremely hard to program, as their optimal software mapping is deeply coupled with hardware design which is unwieldy to manual deployment. We propose "Design in Tiles (DiT)", an automated framework connecting a deployment toolchain with a configurable executable model for these accelerators. For evaluation, we apply our framework to GEMM targeting a large acceleration configuration (e.g., 32x32 tiles, 1979 TFLOPS@FP8, 4 TB/s Bandwidth) comparable to an NVIDIA GH200. We achieve higher PE utilization than GH200 with its expert-tuned GEMM libraries, achieving 1.2-2.0x speedup across diverse matrix shapes. |
| title | Design in Tiles: Automating GEMM Deployment on Tile-Based Many-PE Accelerators |
| topic | Distributed, Parallel, and Cluster Computing Hardware Architecture |
| url | https://arxiv.org/abs/2512.13638 |