Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
Fuente:
arXiv
Saved in:
| Main Authors: | Huo, Juncheng, Gao, Yunfan, Liu, Xinxin, Wang, Sa, Bao, Yungang, Gao, Xitong, Shi, Kan |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
by: Zhong, Yang, et al.
Published: (2025)
by: Zhong, Yang, et al.
Published: (2025)
FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)
by: Qin, Kun, et al.
Published: (2025)
Functional ISS-Driven Verification of Superscalar RISC-V Processors
by: Galimberti, Andrea, et al.
Published: (2024)
by: Galimberti, Andrea, et al.
Published: (2024)
SimFuzz: Similarity-guided Block-level Mutation for RISC-V Processor Fuzzing
by: Lyu, Hao, et al.
Published: (2026)
by: Lyu, Hao, et al.
Published: (2026)
Web-Based Simulator of Superscalar RISC-V Processors
by: Jaros, Jiri, et al.
Published: (2024)
by: Jaros, Jiri, et al.
Published: (2024)
Hypervisor Extension for a RISC-V Processor
by: Gauchola, Jaume, et al.
Published: (2024)
by: Gauchola, Jaume, et al.
Published: (2024)
Floating Point HUB Adder for RISC-V Sargantana Processor
by: Bandera, Gerardo, et al.
Published: (2024)
by: Bandera, Gerardo, et al.
Published: (2024)
Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
by: Rezunov, Evgenii, et al.
Published: (2025)
by: Rezunov, Evgenii, et al.
Published: (2025)
Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
by: Titopoulos, Vasileios, et al.
Published: (2025)
by: Titopoulos, Vasileios, et al.
Published: (2025)
Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)
Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach
by: Ganti, Ravindra, et al.
Published: (2025)
by: Ganti, Ravindra, et al.
Published: (2025)
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)
by: Ottaviano, Alessandro, et al.
Published: (2023)
Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects
by: Ramsauer, Ralf, et al.
Published: (2022)
by: Ramsauer, Ralf, et al.
Published: (2022)
Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
by: Colagrande, Luca, et al.
Published: (2025)
by: Colagrande, Luca, et al.
Published: (2025)
Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
by: McDougall, Ian, et al.
Published: (2025)
by: McDougall, Ian, et al.
Published: (2025)
Bridging the Gap between Hardware Fuzzing and Industrial Verification
by: Ma, Ruiyang, et al.
Published: (2025)
by: Ma, Ruiyang, et al.
Published: (2025)
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training
by: Wang, Yipeng, et al.
Published: (2025)
by: Wang, Yipeng, et al.
Published: (2025)
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference
by: Wang, Chuanning, et al.
Published: (2024)
by: Wang, Chuanning, et al.
Published: (2024)
Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
by: Wang, Weiying, et al.
Published: (2026)
by: Wang, Weiying, et al.
Published: (2026)
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
by: Ahmed, Sajjad, et al.
Published: (2026)
by: Ahmed, Sajjad, et al.
Published: (2026)
Flexing RISC-V Instruction Subset Processors to Extreme Edge
by: Raisiardali, Alireza, et al.
Published: (2025)
by: Raisiardali, Alireza, et al.
Published: (2025)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)
by: Chen, Lu, et al.
Published: (2025)
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
by: Rogenmoser, Michael, et al.
Published: (2024)
by: Rogenmoser, Michael, et al.
Published: (2024)
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference
by: Wang, Chuanning, et al.
Published: (2024)
by: Wang, Chuanning, et al.
Published: (2024)
MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
by: Kirschner, Maximilian, et al.
Published: (2025)
by: Kirschner, Maximilian, et al.
Published: (2025)
Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor
by: Kirschner, Maximilian, et al.
Published: (2024)
by: Kirschner, Maximilian, et al.
Published: (2024)
Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
by: Pu, Huanzhi, et al.
Published: (2025)
by: Pu, Huanzhi, et al.
Published: (2025)
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
by: Perotti, Matteo, et al.
Published: (2022)
by: Perotti, Matteo, et al.
Published: (2022)
Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core
by: Xue, Bing, et al.
Published: (2024)
by: Xue, Bing, et al.
Published: (2024)
Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension
by: Jiang, Limin, et al.
Published: (2025)
by: Jiang, Limin, et al.
Published: (2025)
Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
by: Pham, Anh Kiet, et al.
Published: (2026)
by: Pham, Anh Kiet, et al.
Published: (2026)
MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration
by: Armeniakos, Giorgos, et al.
Published: (2025)
by: Armeniakos, Giorgos, et al.
Published: (2025)
FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
by: Gadde, Deepak Narayan, et al.
Published: (2024)
by: Gadde, Deepak Narayan, et al.
Published: (2024)
Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications
by: Sharma, Vijay Pratap, et al.
Published: (2026)
by: Sharma, Vijay Pratap, et al.
Published: (2026)
MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
by: M, Ajay Kumar, et al.
Published: (2025)
by: M, Ajay Kumar, et al.
Published: (2025)
AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
by: Purayil, Navaneeth Kunhi, et al.
Published: (2025)
by: Purayil, Navaneeth Kunhi, et al.
Published: (2025)
NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16
by: Schmulbach, Viansa, et al.
Published: (2025)
by: Schmulbach, Viansa, et al.
Published: (2025)
CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
by: and, Yan-Cheng Guo, et al.
Published: (2025)
by: and, Yan-Cheng Guo, et al.
Published: (2025)
Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips
by: Koenig, Cyril, et al.
Published: (2025)
by: Koenig, Cyril, et al.
Published: (2025)
Optimization of a Line Detection Algorithm for Autonomous Vehicles on a RISC-V with Accelerator
by: Belda, María José, et al.
Published: (2024)
by: Belda, María José, et al.
Published: (2024)
Similar Items
-
TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
by: Zhong, Yang, et al.
Published: (2025) -
FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025) -
Functional ISS-Driven Verification of Superscalar RISC-V Processors
by: Galimberti, Andrea, et al.
Published: (2024) -
SimFuzz: Similarity-guided Block-level Mutation for RISC-V Processor Fuzzing
by: Lyu, Hao, et al.
Published: (2026) -
Web-Based Simulator of Superscalar RISC-V Processors
by: Jaros, Jiri, et al.
Published: (2024)