Cover Image

ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Zhang, Qijun, Liu, Shang, Lu, Yao, Li, Mengming, Xie, Zhiyao
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
by: Zhang, Qijun, et al.
Published: (2025)

ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
by: Zhang, Qijun, et al.
Published: (2025)

FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
by: Zhang, Qijun, et al.
Published: (2024)

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
by: Li, Mengming, et al.
Published: (2024)

Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
by: Li, Mengming, et al.
Published: (2025)

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
by: Li, Wenkai, et al.
Published: (2025)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)

Profile-Guided Temporal Prefetching
by: Li, Mengming, et al.
Published: (2025)

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
by: Li, Mengming, et al.
Published: (2026)

Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations
by: Zhang, Qijun, et al.
Published: (2024)

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Yan, Zhiyuan, et al.
Published: (2024)

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Fang, Wenji, et al.
Published: (2024)

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
by: Liu, Shang, et al.
Published: (2023)

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
by: Fang, Wenji, et al.
Published: (2025)

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
by: Fang, Wenji, et al.
Published: (2024)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
by: Fang, Wenji, et al.
Published: (2025)

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
by: Fang, Wenji, et al.
Published: (2025)

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
by: Fang, Wenji, et al.
Published: (2025)

Workload-Aware Early-Stage Power Delivery Network Optimization via Architectural Power Traces
by: Hayes, Oran, et al.
Published: (2026)

Power- and Area-Efficient Unary Sorting Architecture Using FSM-Based Unary Number Generator
by: Jalilvand, Amir Hossein, et al.
Published: (2025)

M100: An Orchestrated Dataflow Architecture Powering General AI Computing
by: Xie, Yan, et al.
Published: (2026)

PowerGenie: Analytically-Guided Evolutionary Discovery of Superior Reconfigurable Power Converters
by: Gao, Jian, et al.
Published: (2026)

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)

ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
by: Xie, Tong, et al.
Published: (2025)

EnergAIzer: Fast and Accurate GPU Power Estimation Framework for AI Workloads
by: Lee, Kyungmi, et al.
Published: (2026)

DRIFT: Harnessing Inherent Fault Tolerance for Efficient and Reliable Diffusion Model Inference
by: Wen, Jinqi, et al.
Published: (2026)

A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells
by: Dizabadi, Naser Khatti, et al.
Published: (2026)

An Analytical and Empirical Investigation of Tag Partitioning for Energy-Efficient Reliable Cache
by: Cheshmikhani, Elham, et al.
Published: (2025)

The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization
by: Li, Meng, et al.
Published: (2026)

Enhanced Hybrid Temporal Computing Using Deterministic Summations for Ultra-Low-Power Accelerators
by: Sachdeva, Sachin, et al.
Published: (2025)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)

PowerFlow-DNN: Compiler-Directed Fine-Grained Power Orchestration for End-to-End Edge AI Inference
by: Chen, Paul, et al.
Published: (2026)

Near-Memory Architecture for Threshold-Ordinal Surface-Based Corner Detection of Event Cameras
by: Shang, Hongyang, et al.
Published: (2025)

Aging Aware Adaptive Voltage Scaling for Reliable and Efficient AI Accelerators
by: Xie, Tong, et al.
Published: (2026)

An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell Library
by: Kamath, Akshay Karkal, et al.
Published: (2024)

AI Load Dynamics--A Power Electronics Perspective
by: Li, Yuzhuo, et al.
Published: (2025)

ChatEDA: A Large Language Model Powered Autonomous Agent for EDA
by: He, Zhuolun, et al.
Published: (2023)

SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits
by: Shen, Shan, et al.
Published: (2024)

A Power-Efficient Hardware Implementation of L-Mul
by: Chen, Ruiqi, et al.
Published: (2024)

Focus: A Streaming Concentration Architecture for Efficient Vision-Language Models
by: Wei, Chiyue, et al.
Published: (2025)