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| Auteurs principaux: | , , , , |
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| Format: | Preprint |
| Publié: |
2025
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| Sujets: | |
| Accès en ligne: | https://arxiv.org/abs/2512.14642 |
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| _version_ | 1866911402861527040 |
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| author | Raghav, Himadri Singh Maheshwari, Sachin Smart, Mike Foster, Patrick Serb, Alex |
| author_facet | Raghav, Himadri Singh Maheshwari, Sachin Smart, Mike Foster, Patrick Serb, Alex |
| contents | Recent advances in artificial intelligence, coupled with increasing data bandwidth requirements, in applications such as video processing and high-resolution sensing, have created a growing demand for high computational performance under stringent energy constraints, especially for battery-powered and edge devices. To address this, we present a mixed-signal adiabatic capacitive neural network chip, designed in a 130$nm$ CMOS technology, to demonstrate significant energy savings coupled with high image classification accuracy. Our dual-layer hardware chip, incorporating 16 single-cycle multiply-accumulate engines, can reliably distinguish between 4 classes of 8x8 1-bit images, with classification results over 95\%, within 2.7\% of an equivalent software version. Energy measurements reveal average energy savings between 2.1x and 6.8x, compared to an equivalent CMOS capacitive implementation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_14642 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | An Energy-Efficient Adiabatic Capacitive Neural Network Chip Raghav, Himadri Singh Maheshwari, Sachin Smart, Mike Foster, Patrick Serb, Alex Image and Video Processing Recent advances in artificial intelligence, coupled with increasing data bandwidth requirements, in applications such as video processing and high-resolution sensing, have created a growing demand for high computational performance under stringent energy constraints, especially for battery-powered and edge devices. To address this, we present a mixed-signal adiabatic capacitive neural network chip, designed in a 130$nm$ CMOS technology, to demonstrate significant energy savings coupled with high image classification accuracy. Our dual-layer hardware chip, incorporating 16 single-cycle multiply-accumulate engines, can reliably distinguish between 4 classes of 8x8 1-bit images, with classification results over 95\%, within 2.7\% of an equivalent software version. Energy measurements reveal average energy savings between 2.1x and 6.8x, compared to an equivalent CMOS capacitive implementation. |
| title | An Energy-Efficient Adiabatic Capacitive Neural Network Chip |
| topic | Image and Video Processing |
| url | https://arxiv.org/abs/2512.14642 |