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Autori principali: Su, Xiarui, Teng, Xihui, Yu, Yiyang, Yang, Yiming, Shamim, Atif
Natura: Preprint
Pubblicazione: 2025
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Accesso online:https://arxiv.org/abs/2512.18854
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author Su, Xiarui
Teng, Xihui
Yu, Yiyang
Yang, Yiming
Shamim, Atif
author_facet Su, Xiarui
Teng, Xihui
Yu, Yiyang
Yang, Yiming
Shamim, Atif
contents On-chip reconfigurable intelligent surfaces (RIS) are expected to play a vital role in future 6G communication systems. This work proposed a CMOS-compatible on-chip RIS capable of achieving beam steering for the first time. The proposed unit cell design is a combination of a slot, a phase-delay line with VO2, and a ground. Under the two states of the VO2, the unit cell has a 180 deg phase difference at the center frequency, while maintaining reflection magnitudes better than -1.2 dB. Moreover, a 60by60 RIS array based on the present novel unit is designed, demonstrating the beam-steering capability. Finally, to validate the design concept, a prototype is fabricated, and the detailed fabrication process is presented. The measurement result demonstrates a 27.1 dB enhancement between ON and OFF states. The proposed RIS has the advantages of low loss, CMOS-compatibility, providing a foundation for future 6G applications.
format Preprint
id arxiv_https___arxiv_org_abs_2512_18854
institution arXiv
publishDate 2025
record_format arxiv
spellingShingle A 100-GHz CMOS-Compatible RIS-on-Chip Based on Phase-Delay Lines for 6G Applications
Su, Xiarui
Teng, Xihui
Yu, Yiyang
Yang, Yiming
Shamim, Atif
Signal Processing
On-chip reconfigurable intelligent surfaces (RIS) are expected to play a vital role in future 6G communication systems. This work proposed a CMOS-compatible on-chip RIS capable of achieving beam steering for the first time. The proposed unit cell design is a combination of a slot, a phase-delay line with VO2, and a ground. Under the two states of the VO2, the unit cell has a 180 deg phase difference at the center frequency, while maintaining reflection magnitudes better than -1.2 dB. Moreover, a 60by60 RIS array based on the present novel unit is designed, demonstrating the beam-steering capability. Finally, to validate the design concept, a prototype is fabricated, and the detailed fabrication process is presented. The measurement result demonstrates a 27.1 dB enhancement between ON and OFF states. The proposed RIS has the advantages of low loss, CMOS-compatibility, providing a foundation for future 6G applications.
title A 100-GHz CMOS-Compatible RIS-on-Chip Based on Phase-Delay Lines for 6G Applications
topic Signal Processing
url https://arxiv.org/abs/2512.18854