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| Main Authors: | , , , , , , , , , , , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2512.21330 |
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| _version_ | 1866909975524147200 |
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| author | Athena, Fabia F. Wu, Xiangjin Safron, Nathaniel S. McKeown-Green, Amy Siobhan Dossena, Mauro Evans, Jack C. Hartanto, Jonathan Cho, Yukio Zhong, Donglai Peña, Tara Czaja, Paweł Moradifar, Parivash McIntyre, Paul C. Luisier, Mathieu Cui, Yi Dionne, Jennifer A. Pitner, Greg Radu, Iuliana P. Pop, Eric Salleo, Alberto Wong, H. -S. Philip |
| author_facet | Athena, Fabia F. Wu, Xiangjin Safron, Nathaniel S. McKeown-Green, Amy Siobhan Dossena, Mauro Evans, Jack C. Hartanto, Jonathan Cho, Yukio Zhong, Donglai Peña, Tara Czaja, Paweł Moradifar, Parivash McIntyre, Paul C. Luisier, Mathieu Cui, Yi Dionne, Jennifer A. Pitner, Greg Radu, Iuliana P. Pop, Eric Salleo, Alberto Wong, H. -S. Philip |
| contents | As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$μ$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_21330 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Channel-last gate-all-around nanosheet oxide semiconductor transistors Athena, Fabia F. Wu, Xiangjin Safron, Nathaniel S. McKeown-Green, Amy Siobhan Dossena, Mauro Evans, Jack C. Hartanto, Jonathan Cho, Yukio Zhong, Donglai Peña, Tara Czaja, Paweł Moradifar, Parivash McIntyre, Paul C. Luisier, Mathieu Cui, Yi Dionne, Jennifer A. Pitner, Greg Radu, Iuliana P. Pop, Eric Salleo, Alberto Wong, H. -S. Philip Materials Science As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$μ$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics. |
| title | Channel-last gate-all-around nanosheet oxide semiconductor transistors |
| topic | Materials Science |
| url | https://arxiv.org/abs/2512.21330 |