Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide

Fuente: arXiv

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Bibliographic Details
Main Authors:	Farnaghinejad, Behnam, Porsia, Antonio, Ruospo, Annachiara, Savino, Alessandro, Di Carlo, Stefano, Sanchez, Ernesto
Format:	Preprint
Published:	2025
Subjects:	Cryptography and Security Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2512.21362