Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866915694013054976 |
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| author | Farnaghinejad, Behnam Porsia, Antonio Ruospo, Annachiara Savino, Alessandro Di Carlo, Stefano Sanchez, Ernesto |
| author_facet | Farnaghinejad, Behnam Porsia, Antonio Ruospo, Annachiara Savino, Alessandro Di Carlo, Stefano Sanchez, Ernesto |
| contents | Security in modern RISC-V processors demands more than functional correctness: It requires resilience to side-channel attacks. This paper evaluates the vulnerability of the side channel of the CVA6 RISC-V core by analyzing software-based AES encryption uses an RTL-level power profiling framework called VeriSide. This work represents that this design's Correlation Power Analysis (CPA) reveals significant leakage, enabling key recovery. These findings underscore the importance of early-stage RTL assessments in shaping future secure RISC-V designs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_21362 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide Farnaghinejad, Behnam Porsia, Antonio Ruospo, Annachiara Savino, Alessandro Di Carlo, Stefano Sanchez, Ernesto Cryptography and Security Hardware Architecture Security in modern RISC-V processors demands more than functional correctness: It requires resilience to side-channel attacks. This paper evaluates the vulnerability of the side channel of the CVA6 RISC-V core by analyzing software-based AES encryption uses an RTL-level power profiling framework called VeriSide. This work represents that this design's Correlation Power Analysis (CPA) reveals significant leakage, enabling key recovery. These findings underscore the importance of early-stage RTL assessments in shaping future secure RISC-V designs. |
| title | Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide |
| topic | Cryptography and Security Hardware Architecture |
| url | https://arxiv.org/abs/2512.21362 |