An Energy-Efficient RFET-Based Stochastic Computing Neural Network Accelerator
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866908792962154496 |
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| author | Lu, Sheng Qu, Qianhou Jung, Sungyong Liang, Qilian Pan, Chenyun |
| author_facet | Lu, Sheng Qu, Qianhou Jung, Sungyong Liang, Qilian Pan, Chenyun |
| contents | Stochastic computing (SC) offers significant reductions in hardware complexity for traditional convolutional neural networks(CNNs). However, despite its advantages, stochastic computing neural networks (SCNNs) often suffer from high resource consumption due to components such as stochastic number generators (SNGs) and accumulative parallel counters (APCs), which limit overall performance. This paper proposes a novel SCNN architecture leveraging reconfigurable field-effect transistors (RFETs). The inherent reconfigurability at the device level enables the design of highly efficient and compact SNGs, APCs, and other related essential components. Furthermore, a dedicated SCNN accelerator architecture is developed to facilitate system-level simulation. Based on accessible open-source standard cell libraries, experimental results demonstrate that the proposed RFET-based SCNN accelerator achieves significant reductions in area, latency, and energy consumption compared to its FinFET-based counterpart at the same technology node. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_22131 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | An Energy-Efficient RFET-Based Stochastic Computing Neural Network Accelerator Lu, Sheng Qu, Qianhou Jung, Sungyong Liang, Qilian Pan, Chenyun Hardware Architecture Image and Video Processing Stochastic computing (SC) offers significant reductions in hardware complexity for traditional convolutional neural networks(CNNs). However, despite its advantages, stochastic computing neural networks (SCNNs) often suffer from high resource consumption due to components such as stochastic number generators (SNGs) and accumulative parallel counters (APCs), which limit overall performance. This paper proposes a novel SCNN architecture leveraging reconfigurable field-effect transistors (RFETs). The inherent reconfigurability at the device level enables the design of highly efficient and compact SNGs, APCs, and other related essential components. Furthermore, a dedicated SCNN accelerator architecture is developed to facilitate system-level simulation. Based on accessible open-source standard cell libraries, experimental results demonstrate that the proposed RFET-based SCNN accelerator achieves significant reductions in area, latency, and energy consumption compared to its FinFET-based counterpart at the same technology node. |
| title | An Energy-Efficient RFET-Based Stochastic Computing Neural Network Accelerator |
| topic | Hardware Architecture Image and Video Processing |
| url | https://arxiv.org/abs/2512.22131 |