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| Natura: | Preprint |
| Pubblicazione: |
2025
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| Accesso online: | https://arxiv.org/abs/2512.22676 |
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| _version_ | 1866917172353171456 |
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| author | Salishev, Sergey |
| author_facet | Salishev, Sergey |
| contents | This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a power/energy consumption model for clocked CMOS logic that supports selecting optimal parallelism, (ii) integer-friendly approximation methods for elementary functions that reduce lookup-table size via constrained piecewise-polynomial (quasi-spline) constructions with accuracy guarantees, (iii) provably conflict-free data placement and execution order for mixed-radix streaming FFT on multi-bank and single-port memories, including a self-sorting FFT variant, and (iv) a parallelism/memory analysis of the fast Schur algorithm for superfast Toeplitz system solving, motivated by echo-cancellation workloads. The results provide constructive theorems, schedules, and design trade-offs enabling efficient specialized accelerators. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2512_22676 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Synthesis of signal processing algorithms with constraints on minimal parallelism and memory space Salishev, Sergey Signal Processing Hardware Architecture Distributed, Parallel, and Cluster Computing Numerical Analysis 68W10 (Primary) 65T50, 65D15 (Secondary) B.8.2; F.2.1 This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a power/energy consumption model for clocked CMOS logic that supports selecting optimal parallelism, (ii) integer-friendly approximation methods for elementary functions that reduce lookup-table size via constrained piecewise-polynomial (quasi-spline) constructions with accuracy guarantees, (iii) provably conflict-free data placement and execution order for mixed-radix streaming FFT on multi-bank and single-port memories, including a self-sorting FFT variant, and (iv) a parallelism/memory analysis of the fast Schur algorithm for superfast Toeplitz system solving, motivated by echo-cancellation workloads. The results provide constructive theorems, schedules, and design trade-offs enabling efficient specialized accelerators. |
| title | Synthesis of signal processing algorithms with constraints on minimal parallelism and memory space |
| topic | Signal Processing Hardware Architecture Distributed, Parallel, and Cluster Computing Numerical Analysis 68W10 (Primary) 65T50, 65D15 (Secondary) B.8.2; F.2.1 |
| url | https://arxiv.org/abs/2512.22676 |