ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches
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arXiv
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| Format: | Preprint |
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2026
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| _version_ | 1866915704000741376 |
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| author | Cheshmikhani, Elham Farbeh, Hamed Asadi, Hossein |
| author_facet | Cheshmikhani, Elham Farbeh, Hamed Asadi, Hossein |
| contents | Spin-Transfer Torque Magnetic RAM} (STT-MRAM) is a promising alternative for SRAMs in on-chip cache memories. Besides all its advantages, high error rate in STT-MRAM is a major limiting factor for on-chip cache memories. In this paper, we first present a comprehensive analysis that reveals that the conventional Error-Correcting Codes (ECCs) lose their efficiency due to data-dependent error patterns, and then propose an efficient ECC configuration, so-called ROBIN, to improve the correction capability. The evaluations show that the inefficiency of conventional ECC increases the cache error rate by an average of 151.7% while ROBIN reduces this value by more than 28.6x. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_00456 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches Cheshmikhani, Elham Farbeh, Hamed Asadi, Hossein Hardware Architecture Spin-Transfer Torque Magnetic RAM} (STT-MRAM) is a promising alternative for SRAMs in on-chip cache memories. Besides all its advantages, high error rate in STT-MRAM is a major limiting factor for on-chip cache memories. In this paper, we first present a comprehensive analysis that reveals that the conventional Error-Correcting Codes (ECCs) lose their efficiency due to data-dependent error patterns, and then propose an efficient ECC configuration, so-called ROBIN, to improve the correction capability. The evaluations show that the inefficiency of conventional ECC increases the cache error rate by an average of 151.7% while ROBIN reduces this value by more than 28.6x. |
| title | ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2601.00456 |