Cover Image

ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Cheshmikhani, Elham, Farbeh, Hamed, Asadi, Hossein
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
by: Cheshmikhani, Elham, et al.
Published: (2026)

3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison
by: Cheshmikhani, Elham, et al.
Published: (2025)

An Analytical and Empirical Investigation of Tag Partitioning for Energy-Efficient Reliable Cache
by: Cheshmikhani, Elham, et al.
Published: (2025)

A Low-Cost Reliable Racetrack Cache Based on Data Compression
by: Cheshmikhani, Elham, et al.
Published: (2025)

Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM
by: Hajisadeghi, Amir M., et al.
Published: (2024)

Online Soft Error Tolerance in ReRAM Crossbars for Deep Learning Accelerators
by: Khezeli, Benyamin, et al.
Published: (2024)

SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning
by: Gajaria, Dhruv, et al.
Published: (2024)

Effective and Memory-Efficient Alternatives to ECC for Reliable Large-Scale DNNs
by: Ahmadilivani, Mohammad Hasan, et al.
Published: (2026)

An ECC-based Fault Tolerance Approach for DNNs
by: Raji, Mohsen, et al.
Published: (2025)

ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors
by: Gajaria, Dhruv, et al.
Published: (2024)

Reuse Detector: Improving the Management of STT-RAM SLLCs
by: RodrÍguez-RodrÍguez, Roberto, et al.
Published: (2024)

An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM
by: Yu, Deyang, et al.
Published: (2025)

Cerberus: Cross-Layer ECC Co-Design for Robust and Efficient Memory Protection
by: Kim, Junhwan, et al.
Published: (2026)

HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis
by: SeyedFaraji, Saeed, et al.
Published: (2024)

Modeling and Simulation Frameworks for Processing-in-Memory Architectures
by: Aghaei, Mahdi, et al.
Published: (2025)

Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure
by: Xie, Rui, et al.
Published: (2025)

STT-RAM-based Hierarchical In-Memory Computing
by: Gajaria, Dhruv, et al.
Published: (2024)

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine
by: Prasad, Arpan Suravi, et al.
Published: (2023)

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device
by: Fu, Siqing, et al.
Published: (2023)

Hardware-Efficient CNNs: Interleaved Approximate FP32 Multipliers for Kernel Computation
by: Gowda, Bindu G, et al.
Published: (2025)

A Node-Based Polar List Decoder with Frame Interleaving and Ensemble Decoding Support
by: Ren, Yuqing, et al.
Published: (2024)

Exploring DRAM Cache Prefetching for Pooled Memory
by: Tirumalasetty, Chandrahas, et al.
Published: (2024)

Potential and Limitation of High-Frequency Cores and Caches
by: Pai, Kunal, et al.
Published: (2024)

TDRAM: Tag-enhanced DRAM for Efficient Caching
by: Babaie, Maryam, et al.
Published: (2024)

Fletch: File-System Metadata Caching in Programmable Switches
by: Liu, Qingxiu, et al.
Published: (2025)

Improving the Representativeness of Simulation Intervals for the Cache Memory System
by: Bueno, Nicolas, et al.
Published: (2024)

Spectral Impact of Mismatches in Interleaved ADCs
by: Guichemerre, Jérémy, et al.
Published: (2026)

A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators
by: Narla, Siri, et al.
Published: (2024)

Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing
by: Khadem, Alireza, et al.
Published: (2025)

Pickle Prefetcher: Programmable and Scalable Last-Level Cache Prefetcher
by: Nguyen, Hoa, et al.
Published: (2025)

CMD: A Cache-assisted GPU Memory Deduplication Architecture
by: Zhao, Wei, et al.
Published: (2024)

Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory
by: Hong, Jeongmin, et al.
Published: (2024)

FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications
by: Ranjbar, Ali, et al.
Published: (2025)

Area-Efficient In-Memory Computing for Mixture-of-Experts via Multiplexing and Caching
by: Gao, Hanyuan, et al.
Published: (2026)

3D MPSoC with On-Chip Cache Support -- Design and Exploitation
by: Cataldo, Rodrigo, et al.
Published: (2025)

On the Impact of ISA Extension on Energy Consumption of I-Cache in Extensible Processors
by: Behboudi, Noushin, et al.
Published: (2024)

Titanus: Enabling KV Cache Pruning and Quantization On-the-Fly for LLM Acceleration
by: Chen, Peilin, et al.
Published: (2025)

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
by: Petrolo, Vincenzo, et al.
Published: (2025)

The Open-Source BlackParrot-BedRock Cache Coherence System
by: Wyse, Mark Unruh
Published: (2025)

Choreographer: A Full-System Framework for Fine-Grained Tasks in Cache Hierarchies
by: Nguyen, Hoa, et al.
Published: (2025)