CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version)
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2026
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| _version_ | 1866910034594627584 |
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| author | Lindsay, Nick Trippel, Caroline Khandelwal, Anurag Bhattacharjee, Abhishek |
| author_facet | Lindsay, Nick Trippel, Caroline Khandelwal, Anurag Bhattacharjee, Abhishek |
| contents | Hardware event counters offer the potential to reveal not only performance bottlenecks but also detailed microarchitectural behavior. In practice, this promise is undermined by their vague specifications, opaque designs, and multiplexing noise, making event counter data hard to interpret.
We introduce CounterPoint, a framework that tests user-specified microarchitectural models - expressed as $μ$path Decision Diagrams - for consistency with performance counter data. When mismatches occur, CounterPoint pinpoints plausible microarchitectural features that could explain them, using multi-dimensional counter confidence regions to mitigate multiplexing noise. We apply CounterPoint to the Haswell Memory Management Unit as a case study, shedding light on multiple undocumented and underdocumented microarchitectural behaviors. These include a load-store queue-side TLB prefetcher, merging page table walkers, abortable page table walks, and more.
Overall, CounterPoint helps experts reconcile noisy hardware performance counter measurements with their mental model of the microarchitecture - uncovering subtle, previously hidden hardware features along the way. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_01265 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version) Lindsay, Nick Trippel, Caroline Khandelwal, Anurag Bhattacharjee, Abhishek Hardware Architecture Operating Systems Performance Hardware event counters offer the potential to reveal not only performance bottlenecks but also detailed microarchitectural behavior. In practice, this promise is undermined by their vague specifications, opaque designs, and multiplexing noise, making event counter data hard to interpret. We introduce CounterPoint, a framework that tests user-specified microarchitectural models - expressed as $μ$path Decision Diagrams - for consistency with performance counter data. When mismatches occur, CounterPoint pinpoints plausible microarchitectural features that could explain them, using multi-dimensional counter confidence regions to mitigate multiplexing noise. We apply CounterPoint to the Haswell Memory Management Unit as a case study, shedding light on multiple undocumented and underdocumented microarchitectural behaviors. These include a load-store queue-side TLB prefetcher, merging page table walkers, abortable page table walks, and more. Overall, CounterPoint helps experts reconcile noisy hardware performance counter measurements with their mental model of the microarchitecture - uncovering subtle, previously hidden hardware features along the way. |
| title | CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version) |
| topic | Hardware Architecture Operating Systems Performance |
| url | https://arxiv.org/abs/2601.01265 |