Developments in superconducting erasure qubits for hardware-efficient quantum error correction
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866915722079240192 |
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| author | Violaris, Maria Henaut, Luciana Wills, James Consani, Gioele Friel, Jamie Vlastakis, Brian |
| author_facet | Violaris, Maria Henaut, Luciana Wills, James Consani, Gioele Friel, Jamie Vlastakis, Brian |
| contents | Quantum computers are inherently noisy, and a crucial challenge for achieving large-scale, fault-tolerant quantum computing is to implement quantum error correction. A promising direction that has made rapid recent progress is to design hardware that has a specific noise profile, leading to a significantly higher threshold for noise with certain quantum error correcting codes. This Perspective focuses on erasure qubits, which enable hardware-efficient quantum error correction, by concatenating an inner code built-in to the hardware with an outer code. We focus on implementations of dual-rail encoded erasure qubits using superconducting qubits, giving an overview of recent developments in theory and simulation, and hardware demonstrators. We also discuss the differences between implementations; near-term applications using quantum error detection; and the open problems for developing this approach towards early fault-tolerant quantum computers. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_02183 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Developments in superconducting erasure qubits for hardware-efficient quantum error correction Violaris, Maria Henaut, Luciana Wills, James Consani, Gioele Friel, Jamie Vlastakis, Brian Quantum Physics Quantum computers are inherently noisy, and a crucial challenge for achieving large-scale, fault-tolerant quantum computing is to implement quantum error correction. A promising direction that has made rapid recent progress is to design hardware that has a specific noise profile, leading to a significantly higher threshold for noise with certain quantum error correcting codes. This Perspective focuses on erasure qubits, which enable hardware-efficient quantum error correction, by concatenating an inner code built-in to the hardware with an outer code. We focus on implementations of dual-rail encoded erasure qubits using superconducting qubits, giving an overview of recent developments in theory and simulation, and hardware demonstrators. We also discuss the differences between implementations; near-term applications using quantum error detection; and the open problems for developing this approach towards early fault-tolerant quantum computers. |
| title | Developments in superconducting erasure qubits for hardware-efficient quantum error correction |
| topic | Quantum Physics |
| url | https://arxiv.org/abs/2601.02183 |