Challenges and Research Directions for Large Language Model Inference Hardware
Fuente:
arXiv
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| Hauptverfasser: | , |
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| Format: | Preprint |
| Veröffentlicht: |
2026
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| _version_ | 1866914311607156736 |
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| author | Ma, Xiaoyu Patterson, David |
| author_facet | Ma, Xiaoyu Patterson, David |
| contents | Large Language Model (LLM) inference is hard. The autoregressive Decode phase of the underlying Transformer model makes LLM inference fundamentally different from training. Exacerbated by recent AI trends, the primary challenges are memory and interconnect rather than compute. To address these challenges, we highlight four architecture research opportunities: High Bandwidth Flash for 10X memory capacity with HBM-like bandwidth; Processing-Near-Memory and 3D memory-logic stacking for high memory bandwidth; and low-latency interconnect to speedup communication. While our focus is datacenter AI, we also review their applicability for mobile devices. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_05047 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Challenges and Research Directions for Large Language Model Inference Hardware Ma, Xiaoyu Patterson, David Hardware Architecture Artificial Intelligence Machine Learning Large Language Model (LLM) inference is hard. The autoregressive Decode phase of the underlying Transformer model makes LLM inference fundamentally different from training. Exacerbated by recent AI trends, the primary challenges are memory and interconnect rather than compute. To address these challenges, we highlight four architecture research opportunities: High Bandwidth Flash for 10X memory capacity with HBM-like bandwidth; Processing-Near-Memory and 3D memory-logic stacking for high memory bandwidth; and low-latency interconnect to speedup communication. While our focus is datacenter AI, we also review their applicability for mobile devices. |
| title | Challenges and Research Directions for Large Language Model Inference Hardware |
| topic | Hardware Architecture Artificial Intelligence Machine Learning |
| url | https://arxiv.org/abs/2601.05047 |