Single-Chip 1.024 Tb/s Optical Receiver for High-Speed Optical links
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arXiv
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| Natura: | Preprint |
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2026
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| _version_ | 1866912818577539072 |
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| author | Pirmoradi, Ali Yu, Zhehao Shoobi, Amirreza Ahn, Geun Ho Vučković, Jelena Aflatouni, Firooz |
| author_facet | Pirmoradi, Ali Yu, Zhehao Shoobi, Amirreza Ahn, Geun Ho Vučković, Jelena Aflatouni, Firooz |
| contents | Integrated optical transceivers, utilizing wavelength-division-multiplexing, offer a path forward for implementation of compact, high-bandwidth and energy-efficient interconnects for future data centers. Here we report the demonstration of a monolithically integrated optical receiver in 45nm CMOS, where efficient multi-layer optical demultiplexing with capacitive tuning, energy efficient electronics and wideband inverse designed grating couplers enable implementation of a 32-channel receiver chip based on wavelength-division multiplexing. The chip operates at an aggregate data-rate of 1.024 Tb/s with all channels operating simultaneously at a data-rate of 32 Gb/s/channel achieving a record energy efficiency of 71 fJ/b, including the power consumption of both the electronic circuitry and the tuning and control of photonic devices, and a record bandwidth density of 4 Tb/s/mm2. The receiver achieves a bit-error-rate below 1E-12 without requiring equalization, error correction or digital processing. Inverse-designed broadband grating couplers provide efficient, low-loss optical coupling into the chip. An on-chip demultiplexer, composed of Mach-Zehnder interferometers (MZIs) and ring resonators, offers a large channel-to-channel isolation sufficient for error-free operation. Capacitive phase shifters embedded within the ring resonators of the demultiplexer are used for wavelength alignment at a zero static power consumption. MZIs and ring-resonators are periodically selected and autonomously locked to the wavelength of the corresponding optical carrier. The implemented monolithic receiver offers a scalable, energy-efficient and reliable solution for the beyond Tb/s optical interconnects. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_07709 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Single-Chip 1.024 Tb/s Optical Receiver for High-Speed Optical links Pirmoradi, Ali Yu, Zhehao Shoobi, Amirreza Ahn, Geun Ho Vučković, Jelena Aflatouni, Firooz Optics Applied Physics Integrated optical transceivers, utilizing wavelength-division-multiplexing, offer a path forward for implementation of compact, high-bandwidth and energy-efficient interconnects for future data centers. Here we report the demonstration of a monolithically integrated optical receiver in 45nm CMOS, where efficient multi-layer optical demultiplexing with capacitive tuning, energy efficient electronics and wideband inverse designed grating couplers enable implementation of a 32-channel receiver chip based on wavelength-division multiplexing. The chip operates at an aggregate data-rate of 1.024 Tb/s with all channels operating simultaneously at a data-rate of 32 Gb/s/channel achieving a record energy efficiency of 71 fJ/b, including the power consumption of both the electronic circuitry and the tuning and control of photonic devices, and a record bandwidth density of 4 Tb/s/mm2. The receiver achieves a bit-error-rate below 1E-12 without requiring equalization, error correction or digital processing. Inverse-designed broadband grating couplers provide efficient, low-loss optical coupling into the chip. An on-chip demultiplexer, composed of Mach-Zehnder interferometers (MZIs) and ring resonators, offers a large channel-to-channel isolation sufficient for error-free operation. Capacitive phase shifters embedded within the ring resonators of the demultiplexer are used for wavelength alignment at a zero static power consumption. MZIs and ring-resonators are periodically selected and autonomously locked to the wavelength of the corresponding optical carrier. The implemented monolithic receiver offers a scalable, energy-efficient and reliable solution for the beyond Tb/s optical interconnects. |
| title | Single-Chip 1.024 Tb/s Optical Receiver for High-Speed Optical links |
| topic | Optics Applied Physics |
| url | https://arxiv.org/abs/2601.07709 |