Saved in:
| Main Authors: | Siddens, Sean, Srivastava, Sanya, Levine, Reese, Dykstra, Josiah, Sorensen, Tyler |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2601.08770 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory
by: Bostanci, F. Nisa, et al.
Published: (2024)
by: Bostanci, F. Nisa, et al.
Published: (2024)
PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching
by: Jiang, Fang, et al.
Published: (2024)
by: Jiang, Fang, et al.
Published: (2024)
CipherGuard: Compiler-aided Mitigation against Ciphertext Side-channel Attacks
by: Jiang, Ke, et al.
Published: (2025)
by: Jiang, Ke, et al.
Published: (2025)
Side-channel Inference of User Activities in AR/VR Using GPU Profiling
by: Son, Seonghun, et al.
Published: (2025)
by: Son, Seonghun, et al.
Published: (2025)
PoSyn: Secure Power Side-Channel Aware Synthesis
by: Srivastava, Amisha, et al.
Published: (2025)
by: Srivastava, Amisha, et al.
Published: (2025)
Secure Scattered Memory: Rethinking Secure Enclave Memory with Secret Sharing
by: Geng, Haoran, et al.
Published: (2024)
by: Geng, Haoran, et al.
Published: (2024)
PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference
by: Narkthong, Nuntipat, et al.
Published: (2025)
by: Narkthong, Nuntipat, et al.
Published: (2025)
Empowering Malware Detection Efficiency within Processing-in-Memory Architecture
by: Kasarapu, Sreenitha, et al.
Published: (2024)
by: Kasarapu, Sreenitha, et al.
Published: (2024)
DASICS White Paper: Enhancing Memory Protection with Dynamic Compartmentalization
by: Jin, Yue, et al.
Published: (2023)
by: Jin, Yue, et al.
Published: (2023)
DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands
by: Nam, Hwayong, et al.
Published: (2024)
by: Nam, Hwayong, et al.
Published: (2024)
Descriptor-Based Object-Aware Memory Systems: A Comprehensive Review
by: Tong, Dong
Published: (2025)
by: Tong, Dong
Published: (2025)
Theodosian: A Deep Dive into Memory-Hierarchy-Centric FHE Acceleration
by: Choi, Wonseok, et al.
Published: (2025)
by: Choi, Wonseok, et al.
Published: (2025)
Toleo: Scaling Freshness to Tera-scale Memory using CXL and PIM
by: Dong, Juechu, et al.
Published: (2024)
by: Dong, Juechu, et al.
Published: (2024)
Reliability Analysis of Fully Homomorphic Encryption Systems Under Memory Faults
by: Rajagede, Rian Adam, et al.
Published: (2025)
by: Rajagede, Rian Adam, et al.
Published: (2025)
Space-Control: Process-Level Isolation for Sharing CXL-based Disaggregated Memory
by: Goswami, Kaustav, et al.
Published: (2026)
by: Goswami, Kaustav, et al.
Published: (2026)
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
by: Ye, Haojie, et al.
Published: (2024)
by: Ye, Haojie, et al.
Published: (2024)
Citadel: Simple Spectre-Safe Isolation For Real-World Programs That Share Memory
by: Drean, Jules, et al.
Published: (2023)
by: Drean, Jules, et al.
Published: (2023)
Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes
by: Madabhushi, Bharadwaj, et al.
Published: (2024)
by: Madabhushi, Bharadwaj, et al.
Published: (2024)
Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide
by: Farnaghinejad, Behnam, et al.
Published: (2025)
by: Farnaghinejad, Behnam, et al.
Published: (2025)
Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2023)
by: Olgun, Ataberk, et al.
Published: (2023)
Exploiting Inaccurate Branch History in Side-Channel Attacks
by: Zhu, Yuhui, et al.
Published: (2025)
by: Zhu, Yuhui, et al.
Published: (2025)
DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking assisted Processor Fuzzing
by: Xu, Jinyan, et al.
Published: (2025)
by: Xu, Jinyan, et al.
Published: (2025)
Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking
by: Li, Weihang, et al.
Published: (2025)
by: Li, Weihang, et al.
Published: (2025)
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs
by: Galli, Davide, et al.
Published: (2024)
by: Galli, Davide, et al.
Published: (2024)
RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
by: Pinto, Sandro, et al.
Published: (2024)
by: Pinto, Sandro, et al.
Published: (2024)
PhantomFetch: Obfuscating Loads against Prefetcher Side-Channel Attacks
by: Zhang, Xingzhi, et al.
Published: (2025)
by: Zhang, Xingzhi, et al.
Published: (2025)
Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
by: Bostancı, F. Nisa, et al.
Published: (2025)
by: Bostancı, F. Nisa, et al.
Published: (2025)
RollingCache: Using Runtime Behavior to Defend Against Cache Side Channel Attacks
by: Ojha, Divya, et al.
Published: (2024)
by: Ojha, Divya, et al.
Published: (2024)
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024)
by: Zoni, Davide, et al.
Published: (2024)
ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
by: Narkthong, Nuntipat, et al.
Published: (2025)
by: Narkthong, Nuntipat, et al.
Published: (2025)
TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
by: Liu, Yuntao, et al.
Published: (2023)
by: Liu, Yuntao, et al.
Published: (2023)
THOR: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX
by: Dizani, Farshad, et al.
Published: (2025)
by: Dizani, Farshad, et al.
Published: (2025)
Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography
by: Baidya, Paresh, et al.
Published: (2025)
by: Baidya, Paresh, et al.
Published: (2025)
Case Study: Horizontal Side-Channel Analysis Attack against Elliptic Curve Scalar Multiplication Accelerator under Laser Illumination
by: Petryk, Dmytro, et al.
Published: (2026)
by: Petryk, Dmytro, et al.
Published: (2026)
DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
by: Hassan, Muhammad, et al.
Published: (2025)
by: Hassan, Muhammad, et al.
Published: (2025)
In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
by: Ovy, Sanwar Ahmed, et al.
Published: (2025)
by: Ovy, Sanwar Ahmed, et al.
Published: (2025)
PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption
by: Tan, Weihang, et al.
Published: (2023)
by: Tan, Weihang, et al.
Published: (2023)
Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators
by: Weerasena, Hansika, et al.
Published: (2023)
by: Weerasena, Hansika, et al.
Published: (2023)
ABC-FHE : A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption
by: Yune, Sungwoong, et al.
Published: (2025)
by: Yune, Sungwoong, et al.
Published: (2025)
DARTH-PUM: A Hybrid Processing-Using-Memory Architecture
by: Wong, Ryan, et al.
Published: (2026)
by: Wong, Ryan, et al.
Published: (2026)
Similar Items
-
Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory
by: Bostanci, F. Nisa, et al.
Published: (2024) -
PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching
by: Jiang, Fang, et al.
Published: (2024) -
CipherGuard: Compiler-aided Mitigation against Ciphertext Side-channel Attacks
by: Jiang, Ke, et al.
Published: (2025) -
Side-channel Inference of User Activities in AR/VR Using GPU Profiling
by: Son, Seonghun, et al.
Published: (2025) -
PoSyn: Secure Power Side-Channel Aware Synthesis
by: Srivastava, Amisha, et al.
Published: (2025)