Cover Image

NuRedact: Non-Uniform eFPGA Architecture for Low-Overhead and Secure IP Redaction

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Das, Voktho, Azar, Kimia, Kamali, Hadi
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture Cryptography and Security
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

REDACTOR: eFPGA Redaction for DNN Accelerator Security
by: Baddour, Yazan, et al.
Published: (2025)

Secure eFPGA-Enabled Edge LLM Inference: Architectural and Hardware Countermeasures
by: Das, Voktho, et al.
Published: (2026)

SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation
by: Rezakhani, Mahshid, et al.
Published: (2026)

From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
by: Mashnoor, Nowfel, et al.
Published: (2026)

Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance
by: Canpolat, Oğuzhan, et al.
Published: (2024)

FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption
by: Xu, Zhihan, et al.
Published: (2025)

ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation
by: Olgun, Ataberk, et al.
Published: (2023)

An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024)

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
by: Collini, Luca, et al.
Published: (2025)

Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
by: Pham, Anh Kiet, et al.
Published: (2026)

Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
by: Raj, Kshitij, et al.
Published: (2025)

Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads
by: Kim, Jumin, et al.
Published: (2025)

Formal Verification of Secure Encrypted Virtualization
by: Weerasena, Hansika, et al.
Published: (2026)

Efficient and Lightweight In-memory Computing Architecture for Hardware Security
by: Ajmi, Hala, et al.
Published: (2022)

The Avatar Cache: Enabling On-Demand Security with Morphable Cache Architecture
by: Bhatla, Anubhav, et al.
Published: (2026)

ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits
by: Sekanina, Lukas, et al.
Published: (2026)

Logistic Map Pseudo Random Number Generator in FPGA
by: Calderon, Mateo Jalen Andrew, et al.
Published: (2024)

Low-Complexity Integer Divider Architecture for Homomorphic Encryption
by: Akherati, Sajjad, et al.
Published: (2024)

if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs
by: Butt, Shahzad Ahmad, et al.
Published: (2024)

Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures
by: Halder, Dipal
Published: (2023)

ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection
by: Zhang, Ruisi, et al.
Published: (2024)

Efficient Hardware Implementation of Modular Multiplier over GF (2m) on FPGA
by: Kumari, Ruby, et al.
Published: (2025)

PUFBind: PUF-Enabled Lightweight Program Binary Authentication for FPGA-based Embedded Systems
by: Swaroopa, Sneha, et al.
Published: (2025)

Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography
by: Baidya, Paresh, et al.
Published: (2025)

DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2022)

History-Aware Trajectory k-Anonymization Using an FPGA-Based Hardware Accelerator for Real-Time Location Services
by: Nakano, Hiroshi, et al.
Published: (2025)

High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
by: Amael, Joshua Tito, et al.
Published: (2024)

Secure Scattered Memory: Rethinking Secure Enclave Memory with Secret Sharing
by: Geng, Haoran, et al.
Published: (2024)

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures
by: Weerasena, Hansika, et al.
Published: (2026)

Supporting Secured Integration of Microarchitectural Defenses
by: Ramkrishnan, Kartik, et al.
Published: (2026)

Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024)

On the Importance of Reproducibility of Experimental Results Especially in the Domain of Security
by: Petryk, Dmytro, et al.
Published: (2024)

Modern Hardware Security: A Review of Attacks and Countermeasures
by: Mishra, Jyotiprakash, et al.
Published: (2025)

New Security Challenges Towards In-Sensor Computing Systems
by: Kajol, Mashrafi, et al.
Published: (2025)

GPU in the Blind Spot: Overlooked Security Risks in Transportation
by: Puspa, Sefatun-Noor, et al.
Published: (2025)

A Near-Cache Architectural Framework for Cryptographic Computing
by: Zhang, Jingyao, et al.
Published: (2025)

MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker
by: Qureshi, Moinuddin, et al.
Published: (2024)

CIBPU: A Conflict-Invisible Secure Branch Prediction Unit
by: Zhou, Zhe, et al.
Published: (2025)

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
by: Mulhem, Saleh, et al.
Published: (2024)

Fastrack: Fast IO for Secure ML using GPU TEEs
by: Wang, Yongqin, et al.
Published: (2024)