Biological Intuition on Digital Hardware: An RTL Implementation of Poisson-Encoded SNNs for Static Image Classification
Fuente:
arXiv
Saved in:
| Main Authors: | Das, Debabrata, K., Yogeeth G., Gupta, Arnav |
|---|---|
| Format: | Preprint |
| Published: |
2026
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Nonvolatile Charge-Domain Attention with HZO Ferroelectric Capacitors: A Simulation-Based Device-to-System Evaluation
by: Abouagour, Faris
Published: (2026)
by: Abouagour, Faris
Published: (2026)
DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
by: Zhang, Yuhan, et al.
Published: (2026)
by: Zhang, Yuhan, et al.
Published: (2026)
GainSight: A Unified Framework for Data Lifetime Profiling and Heterogeneous Memory Composition
by: Li, Peijing, et al.
Published: (2025)
by: Li, Peijing, et al.
Published: (2025)
TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence
by: Guan, Hongyi, et al.
Published: (2026)
by: Guan, Hongyi, et al.
Published: (2026)
NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices
by: Fu, Siqing, et al.
Published: (2025)
by: Fu, Siqing, et al.
Published: (2025)
A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
by: Aspros, Maxime Henri, et al.
Published: (2025)
by: Aspros, Maxime Henri, et al.
Published: (2025)
OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
by: Lebold, Denis, et al.
Published: (2026)
by: Lebold, Denis, et al.
Published: (2026)
RayFlex: An Open-Source RTL Implementation of the Hardware Ray Tracer Datapath
by: Shen, Fangjia, et al.
Published: (2024)
by: Shen, Fangjia, et al.
Published: (2024)
Design and Implementation of an FPGA-Based Hardware Accelerator for Transformer
by: Li, Richie, et al.
Published: (2025)
by: Li, Richie, et al.
Published: (2025)
Time Domain Near Memory Computing Engine
by: Antal, Sarthak, et al.
Published: (2026)
by: Antal, Sarthak, et al.
Published: (2026)
Minimal Neuron Circuits -- Part I: Resonators
by: Nabil, Amr, et al.
Published: (2025)
by: Nabil, Amr, et al.
Published: (2025)
Minimal Neuron Circuits: Bursters
by: Nabil, Amr, et al.
Published: (2025)
by: Nabil, Amr, et al.
Published: (2025)
RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
by: Yildirim, Muhammed, et al.
Published: (2025)
by: Yildirim, Muhammed, et al.
Published: (2025)
Dataflow & Tiling Strategies in Edge-AI FPGA Accelerators: A Comprehensive Literature Review
by: Li, Richie
Published: (2025)
by: Li, Richie
Published: (2025)
basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I
by: Kang, Hyun Woo, et al.
Published: (2025)
by: Kang, Hyun Woo, et al.
Published: (2025)
CGRA4ML: A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing
by: Abarajithan, G, et al.
Published: (2024)
by: Abarajithan, G, et al.
Published: (2024)
RISCBench: Benchmarking RISC-V Orchestration Efficiency in FPGA and FPGA-Like Computing Engines
by: Ojika, Dave, et al.
Published: (2025)
by: Ojika, Dave, et al.
Published: (2025)
RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures
by: Kang, Hyunwoo
Published: (2026)
by: Kang, Hyunwoo
Published: (2026)
Toward Thermodynamic Reservoir Computing: Exploring SHA-256 ASICs as Potential Physical Substrates
by: de Lafuente, Francisco Angulo, et al.
Published: (2026)
by: de Lafuente, Francisco Angulo, et al.
Published: (2026)
A 65 nm Bayesian Neural Network Accelerator with 360 fJ/Sample In-Word GRNG for AI Uncertainty Estimation
by: Enciso, Zephan M., et al.
Published: (2025)
by: Enciso, Zephan M., et al.
Published: (2025)
FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
by: Parameshwara, Arya, et al.
Published: (2025)
by: Parameshwara, Arya, et al.
Published: (2025)
ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs
by: Tashdid, Ishraq, et al.
Published: (2025)
by: Tashdid, Ishraq, et al.
Published: (2025)
Lean Attention: Hardware-Aware Scalable Attention Mechanism for the Decode-Phase of Transformers
by: Sanovar, Rya, et al.
Published: (2024)
by: Sanovar, Rya, et al.
Published: (2024)
Photonic AI: A Hybrid Diffractive Holographic Neural System for Passive Optical Real-Time Image Classification
by: Hiremath, Prakul Sunil
Published: (2026)
by: Hiremath, Prakul Sunil
Published: (2026)
InterPUF: Distributed Authentication via Physically Unclonable Functions and Multi-party Computation for Reconfigurable Interposers
by: Tashdid, Ishraq, et al.
Published: (2026)
by: Tashdid, Ishraq, et al.
Published: (2026)
SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration
by: Parameshwara, Arya
Published: (2025)
by: Parameshwara, Arya
Published: (2025)
TokenStack: A Heterogeneous HBM-PIM Architecture and Runtime for Efficient LLM Inference
by: Li, Zhuoran, et al.
Published: (2026)
by: Li, Zhuoran, et al.
Published: (2026)
ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
by: Eryilmaz, Cagri
Published: (2026)
by: Eryilmaz, Cagri
Published: (2026)
Differentiable Logic Synthesis: Spectral Coefficient Selection via Sinkhorn-Constrained Composition
by: Pavlov, Gorgi
Published: (2026)
by: Pavlov, Gorgi
Published: (2026)
Multi-diseases detection with memristive system on chip
by: Wang, Zihan, et al.
Published: (2024)
by: Wang, Zihan, et al.
Published: (2024)
An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation
by: Qiu, Ruizhi, et al.
Published: (2025)
by: Qiu, Ruizhi, et al.
Published: (2025)
Speaking to Silicon: Neural Communication with Bitcoin Mining ASICs
by: de Lafuente, Francisco Angulo, et al.
Published: (2026)
by: de Lafuente, Francisco Angulo, et al.
Published: (2026)
FlexiBit: Fully Flexible Precision Bit-parallel Accelerator Architecture for Arbitrary Mixed Precision AI
by: Tahmasebi, Faraz, et al.
Published: (2024)
by: Tahmasebi, Faraz, et al.
Published: (2024)
Automated Hardware Trojan Insertion in Industrial-Scale Designs
by: Popryho, Yaroslav, et al.
Published: (2025)
by: Popryho, Yaroslav, et al.
Published: (2025)
Static Communication Analysis for Hardware Design
by: Rosendahl, Mads, et al.
Published: (2025)
by: Rosendahl, Mads, et al.
Published: (2025)
Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
by: Chen, Mu-Chi, et al.
Published: (2026)
by: Chen, Mu-Chi, et al.
Published: (2026)
PilotBench: A Benchmark for General Aviation Agents with Safety Constraints
by: Wu, Yalun, et al.
Published: (2026)
by: Wu, Yalun, et al.
Published: (2026)
Fast and Practical Strassen's Matrix Multiplication using FPGAs
by: Ahmad, Afzal, et al.
Published: (2024)
by: Ahmad, Afzal, et al.
Published: (2024)
Non-interfering On-line and In-field SoC Testing
by: Strauch, Tobias
Published: (2024)
by: Strauch, Tobias
Published: (2024)
Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM
by: Liu, Lian, et al.
Published: (2025)
by: Liu, Lian, et al.
Published: (2025)
Similar Items
-
Nonvolatile Charge-Domain Attention with HZO Ferroelectric Capacitors: A Simulation-Based Device-to-System Evaluation
by: Abouagour, Faris
Published: (2026) -
DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
by: Zhang, Yuhan, et al.
Published: (2026) -
GainSight: A Unified Framework for Data Lifetime Profiling and Heterogeneous Memory Composition
by: Li, Peijing, et al.
Published: (2025) -
TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence
by: Guan, Hongyi, et al.
Published: (2026) -
NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices
by: Fu, Siqing, et al.
Published: (2025)