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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2026
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2601.14087 |
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| _version_ | 1866915740741795840 |
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| author | Han, Ruichi Chen, Yizhi Lei, Tong Gonzalez, Jordi Altayo Hemani, Ahmed |
| author_facet | Han, Ruichi Chen, Yizhi Lei, Tong Gonzalez, Jordi Altayo Hemani, Ahmed |
| contents | Interconnect power consumption remains a bottleneck in Deep Neural Network (DNN) accelerators. While ordering data based on '1'-bit counts can mitigate this via reduced switching activity, practical hardware sorting implementations remain underexplored. This work proposes the hardware implementation of a comparison-free sorting unit optimized for Convolutional Neural Networks (CNN). By leveraging approximate computing to group population counts into coarse-grained buckets, our design achieves hardware area reductions while preserving the link power benefits of data reordering. Our approximate sorting unit achieves up to 35.4% area reduction while maintaining 19.50\% BT reduction compared to 20.42% of precise implementation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_14087 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | '1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators Han, Ruichi Chen, Yizhi Lei, Tong Gonzalez, Jordi Altayo Hemani, Ahmed Hardware Architecture Artificial Intelligence Machine Learning Interconnect power consumption remains a bottleneck in Deep Neural Network (DNN) accelerators. While ordering data based on '1'-bit counts can mitigate this via reduced switching activity, practical hardware sorting implementations remain underexplored. This work proposes the hardware implementation of a comparison-free sorting unit optimized for Convolutional Neural Networks (CNN). By leveraging approximate computing to group population counts into coarse-grained buckets, our design achieves hardware area reductions while preserving the link power benefits of data reordering. Our approximate sorting unit achieves up to 35.4% area reduction while maintaining 19.50\% BT reduction compared to 20.42% of precise implementation. |
| title | '1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators |
| topic | Hardware Architecture Artificial Intelligence Machine Learning |
| url | https://arxiv.org/abs/2601.14087 |