Bit-Efficient Quantisation for Two-Channel Modulo-Sampling Systems
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arXiv
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| Hauptverfasser: | , , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2026
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| _version_ | 1866912835894771712 |
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| author | Yan, Wenyi Li, Zeyuan Gan, Lu Liu, Honqing Li, Guoquan |
| author_facet | Yan, Wenyi Li, Zeyuan Gan, Lu Liu, Honqing Li, Guoquan |
| contents | Two-channel modulo analog-to-digital converters (ADCs) enable high-dynamic-range signal sensing at the Nyquist rate per channel, but existing designs quantise both channel outputs independently, incurring redundant bitrate costs. This paper proposes a bit-efficient quantisation scheme that exploits the integer-valued structure of inter-channel differences, transmitting one quantised channel output together with a compact difference index. We prove that this approach requires only 1-2 bits per signal sample overhead relative to conventional ADCs, despite operating with a much smaller per-channel dynamic range. Simulations confirm the theoretical error bounds and bitrate analysis, while hardware experiments demonstrate substantial bitrate savings compared with existing modulo sampling schemes, while maintaining comparable reconstruction accuracy. These results highlight a practical path towards high-resolution, bandwidth-efficient modulo ADCs for bitrate-constrained systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_14220 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Bit-Efficient Quantisation for Two-Channel Modulo-Sampling Systems Yan, Wenyi Li, Zeyuan Gan, Lu Liu, Honqing Li, Guoquan Signal Processing Two-channel modulo analog-to-digital converters (ADCs) enable high-dynamic-range signal sensing at the Nyquist rate per channel, but existing designs quantise both channel outputs independently, incurring redundant bitrate costs. This paper proposes a bit-efficient quantisation scheme that exploits the integer-valued structure of inter-channel differences, transmitting one quantised channel output together with a compact difference index. We prove that this approach requires only 1-2 bits per signal sample overhead relative to conventional ADCs, despite operating with a much smaller per-channel dynamic range. Simulations confirm the theoretical error bounds and bitrate analysis, while hardware experiments demonstrate substantial bitrate savings compared with existing modulo sampling schemes, while maintaining comparable reconstruction accuracy. These results highlight a practical path towards high-resolution, bandwidth-efficient modulo ADCs for bitrate-constrained systems. |
| title | Bit-Efficient Quantisation for Two-Channel Modulo-Sampling Systems |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2601.14220 |