GNN-based Path-aware multi-view Circuit Learning for Technology Mapping
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866918298073956352 |
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| author | Jiang, Wentao Wang, Jingxin Hu, Zhang Shi, Zhengyuan Ma, Chengyu Xu, Qiang Qian, Weikang Chu, Zhufei |
| author_facet | Jiang, Wentao Wang, Jingxin Hu, Zhang Shi, Zhengyuan Ma, Chengyu Xu, Qiang Qian, Weikang Chu, Zhufei |
| contents | Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_14286 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | GNN-based Path-aware multi-view Circuit Learning for Technology Mapping Jiang, Wentao Wang, Jingxin Hu, Zhang Shi, Zhengyuan Ma, Chengyu Xu, Qiang Qian, Weikang Chu, Zhufei Emerging Technologies Machine Learning Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency. |
| title | GNN-based Path-aware multi-view Circuit Learning for Technology Mapping |
| topic | Emerging Technologies Machine Learning |
| url | https://arxiv.org/abs/2601.14286 |