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| Autores principales: | , |
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| Formato: | Preprint |
| Publicado: |
2026
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| Materias: | |
| Acceso en línea: | https://arxiv.org/abs/2601.14476 |
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| _version_ | 1866918298892894208 |
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| author | Onizawa, Naoya Hanyu, Takahiro |
| author_facet | Onizawa, Naoya Hanyu, Takahiro |
| contents | Probabilistic computing using probabilistic bits (p-bits) presents an efficient alternative to traditional CMOS logic for complex problem-solving, including simulated annealing and machine learning. Realizing p-bits with emerging devices such as magnetic tunnel junctions (MTJs) introduces device variability, which was expected to negatively impact computational performance. However, this study reveals an unexpected finding: device variability can not only degrade but also enhance algorithm performance, particularly by leveraging timing variability. This paper introduces a GPU-accelerated, open-source simulated annealing framework based on p-bits that models key device variability factors -- timing, intensity, and offset -- to reflect real-world device behavior. Through CUDA-based simulations, our approach achieves a two-order magnitude speedup over CPU implementations on the MAX-CUT benchmark with problem sizes ranging from 800 to 20,000 nodes. By providing a scalable and accessible tool, this framework aims to advance research in probabilistic computing, enabling optimization applications in diverse fields. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_14476 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling Onizawa, Naoya Hanyu, Takahiro Machine Learning Artificial Intelligence Probabilistic computing using probabilistic bits (p-bits) presents an efficient alternative to traditional CMOS logic for complex problem-solving, including simulated annealing and machine learning. Realizing p-bits with emerging devices such as magnetic tunnel junctions (MTJs) introduces device variability, which was expected to negatively impact computational performance. However, this study reveals an unexpected finding: device variability can not only degrade but also enhance algorithm performance, particularly by leveraging timing variability. This paper introduces a GPU-accelerated, open-source simulated annealing framework based on p-bits that models key device variability factors -- timing, intensity, and offset -- to reflect real-world device behavior. Through CUDA-based simulations, our approach achieves a two-order magnitude speedup over CPU implementations on the MAX-CUT benchmark with problem sizes ranging from 800 to 20,000 nodes. By providing a scalable and accessible tool, this framework aims to advance research in probabilistic computing, enabling optimization applications in diverse fields. |
| title | GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling |
| topic | Machine Learning Artificial Intelligence |
| url | https://arxiv.org/abs/2601.14476 |