Cover Image

@NTT: Algorithm-Targeted NTT hardware acceleration via Design-Time Constant Optimization

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Nabeel, Mohammed, Hafez, Mahmoud, Maniatakos, Michail
Format:	Preprint
Published:	2026
Subjects:	Cryptography and Security Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption
by: Tan, Weihang, et al.
Published: (2023)

Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
by: Paul, Rourab, et al.
Published: (2026)

HF-NTT: Hazard-Free Dataflow Accelerator for Number Theoretic Transform
by: Meng, Xiangchen, et al.
Published: (2024)

CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution (Extended Version)
by: Nabeel, Mohammed, et al.
Published: (2022)

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics
by: Razmkhah, Sasan, et al.
Published: (2025)

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024)

The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs
by: Galli, Davide, et al.
Published: (2024)

Cost-Effective Optimization and Implementation of the CRT-Paillier Decryption Algorithm for Enhanced Performance
by: Huang, Zhengwu, et al.
Published: (2025)

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
by: Ku, Jonathan, et al.
Published: (2024)

eFPE: Design, Implementation, and Evaluation of a Lightweight Format-Preserving Encryption Algorithm for Embedded Systems
by: Hegde, Nishant Vasantkumar, et al.
Published: (2025)

AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures
by: Fu, Bo, et al.
Published: (2025)

Taiyi: A high-performance CKKS accelerator for Practical Fully Homomorphic Encryption
by: Fan, Shengyu, et al.
Published: (2024)

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
by: Reimann, Lennart M., et al.
Published: (2024)

Targeted Wearout Attacks in Microprocessor Cores
by: Mashburn, Joshua, et al.
Published: (2025)

Enabling Deterministic User-Level Interrupts in Real-Time Processors via Hardware Extension
by: Yang, Hongbin, et al.
Published: (2026)

Algorithms for Improving the Automatically Synthesized Instruction Set of an Extensible Processor
by: Sovietov, Peter
Published: (2024)

An Efficient Algorithm for Modulus Operation and Its Hardware Implementation in Prime Number Calculation
by: Wijesinghe, W. A. Susantha
Published: (2024)

Logic Encryption: This Time for Real
by: Karn, Rupesh Raj, et al.
Published: (2025)

Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024)

The Quest to Build Trust Earlier in Digital Design
by: Tan, Benjamin
Published: (2024)

DSAC: Low-Cost RowHammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm
by: Hong, Seungki, et al.
Published: (2023)

SoK: Systematizing a Decade of Architectural RowHammer Defenses Through the Lens of Streaming Algorithms
by: Kim, Michael Jaemin, et al.
Published: (2025)

Automated Physical Design Watermarking Leveraging Graph Neural Networks
by: Zhang, Ruisi, et al.
Published: (2024)

Systematic Evaluation of Randomized Cache Designs against Cache Occupancy
by: Chakraborty, Anirban, et al.
Published: (2023)

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
by: Wistoff, Nils, et al.
Published: (2022)

Random and Safe Cache Architecture to Defeat Cache Timing Attacks
by: Hu, Guangyuan, et al.
Published: (2023)

BETA: Automated Black-box Exploration for Timing Attacks in Processors
by: Chen, Congcong, et al.
Published: (2024)

Design high-confidence computers using trusted instructional set architecture and emulators
by: Wang, Shuangbao Paul
Published: (2025)

Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
by: Ye, Haojie, et al.
Published: (2024)

ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
by: Sheikh, Ahmad T., et al.
Published: (2024)

Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks
by: Li, Tuo, et al.
Published: (2022)

ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection
by: Zhang, Ruisi, et al.
Published: (2024)

Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study
by: Imtiaz, Sharjeel, et al.
Published: (2025)

Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures
by: Halder, Dipal
Published: (2023)

Shield Bash: Abusing Defensive Coherence State Retrieval to Break Timing Obfuscation
by: Ramkrishnan, Kartik, et al.
Published: (2025)

BOLT: Bandwidth-Optimized Lightning-Fast Oblivious Map powered by Secure HBM Accelerators
by: Guo, Yitong, et al.
Published: (2025)

BackCache: Mitigating Contention-Based Cache Timing Attacks by Hiding Cache Line Evictions
by: Wang, Quancheng, et al.
Published: (2023)

THOR: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX
by: Dizani, Farshad, et al.
Published: (2025)

History-Aware Trajectory k-Anonymization Using an FPGA-Based Hardware Accelerator for Real-Time Location Services
by: Nakano, Hiroshi, et al.
Published: (2025)

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
by: Wang, Zeng, et al.
Published: (2025)