APA (7th ed.) Citation

Shin, D., Onizawa, N., Gross, W. J., & Hanyu, T. (2026). Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing.

Chicago Style (17th ed.) Citation

Shin, Duckgyu, Naoya Onizawa, Warren J. Gross, and Takahiro Hanyu. Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. 2026.

MLA (9th ed.) Citation

Shin, Duckgyu, et al. Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. 2026.