Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2026
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| _version_ | 1866915755307565056 |
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| author | Shin, Duckgyu Onizawa, Naoya Gross, Warren J. Hanyu, Takahiro |
| author_facet | Shin, Duckgyu Onizawa, Naoya Gross, Warren J. Hanyu, Takahiro |
| contents | Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the problem grows. Recently, a stochastic simulated annealing (SSA) algorithm that converges faster than conventional SA has been reported. In this paper, we present a hardware-aware SSA (HA- SSA) algorithm for memory-efficient FPGA implementations. HA-SSA can reduce the memory usage of storing intermediate results while maintaining the computing speed of SSA. For evaluation purposes, the proposed algorithm is compared with the conventional SSA and SA approaches on maximum cut combinatorial optimization problems. HA-SSA achieves a convergence speed that is up to 114-times faster than that of the conventional SA algorithm depending on the maximum cut problem selected from the G-set which is a dataset of the maximum cut problems. HA-SSA is implemented on a field-programmable gate array (FPGA) (Xilinx Kintex-7), and it achieves up to 6-times the memory efficiency of conventional SSA while maintaining high solution quality for optimization problems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_18007 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing Shin, Duckgyu Onizawa, Naoya Gross, Warren J. Hanyu, Takahiro Hardware Architecture Machine Learning Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the problem grows. Recently, a stochastic simulated annealing (SSA) algorithm that converges faster than conventional SA has been reported. In this paper, we present a hardware-aware SSA (HA- SSA) algorithm for memory-efficient FPGA implementations. HA-SSA can reduce the memory usage of storing intermediate results while maintaining the computing speed of SSA. For evaluation purposes, the proposed algorithm is compared with the conventional SSA and SA approaches on maximum cut combinatorial optimization problems. HA-SSA achieves a convergence speed that is up to 114-times faster than that of the conventional SA algorithm depending on the maximum cut problem selected from the G-set which is a dataset of the maximum cut problems. HA-SSA is implemented on a field-programmable gate array (FPGA) (Xilinx Kintex-7), and it achieves up to 6-times the memory efficiency of conventional SSA while maintaining high solution quality for optimization problems. |
| title | Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2601.18007 |