RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version)
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2026
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| _version_ | 1866914280317648896 |
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| author | Zhu, Yan Chen, Boru Fletcher, Christopher W. Nayak, Nandeeka |
| author_facet | Zhu, Yan Chen, Boru Fletcher, Christopher W. Nayak, Nandeeka |
| contents | RTL simulation on CPUs remains a persistent bottleneck in hardware design. State-of-the-art simulators embed the circuit directly into the simulation binary, resulting in long compilation times and execution that is fundamentally CPU frontend-bound, with severe instruction-cache pressure.
This work proposes RTeAAL Sim, which reformulates RTL simulation as a sparse tensor algebra problem. By representing RTL circuits as tensors and simulation as a sparse tensor algebra kernel, RTeAAL Sim decouples simulation behavior from binary size and makes RTL simulation amenable to well-studied tensor algebra optimizations. We demonstrate that a prototype of our tensor-based simulator, even with a subset of these optimizations, already mitigates the compilation overhead and frontend pressure and achieves performance competitive with the highly optimized Verilator simulator across multiple CPUs and ISAs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_18140 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version) Zhu, Yan Chen, Boru Fletcher, Christopher W. Nayak, Nandeeka Hardware Architecture RTL simulation on CPUs remains a persistent bottleneck in hardware design. State-of-the-art simulators embed the circuit directly into the simulation binary, resulting in long compilation times and execution that is fundamentally CPU frontend-bound, with severe instruction-cache pressure. This work proposes RTeAAL Sim, which reformulates RTL simulation as a sparse tensor algebra problem. By representing RTL circuits as tensors and simulation as a sparse tensor algebra kernel, RTeAAL Sim decouples simulation behavior from binary size and makes RTL simulation amenable to well-studied tensor algebra optimizations. We demonstrate that a prototype of our tensor-based simulator, even with a subset of these optimizations, already mitigates the compilation overhead and frontend pressure and achieves performance competitive with the highly optimized Verilator simulator across multiple CPUs and ISAs. |
| title | RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version) |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2601.18140 |