Cover Image

Lifecycle Cost-Effectiveness Modeling for Redundancy-Enhanced Multi-Chiplet Architectures

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Liu, Zizhen, Wang, Fangzhiyi, Wang, Mengdi, Ye, Jing, So, Hayden Kwok-Hay, Liu, Cheng, Li, Huawei
Format:	Preprint
Published:	2026
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA
by: Gao, Yizhao, et al.
Published: (2024)

Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
by: Feng, Yinxiao, et al.
Published: (2022)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
by: Tang, Jiaping, et al.
Published: (2025)

TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture
by: Wu, Jiajun, et al.
Published: (2024)

Extend IVerilog to Support Batch RTL Fault Simulation
by: Tang, Jiaping, et al.
Published: (2025)

RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures
by: Iff, Patrick, et al.
Published: (2023)

Co-designing a Sub-millisecond Latency Event-based Eye Tracking System with Submanifold Sparse CNN
by: Zhang, Baoheng, et al.
Published: (2024)

Monad: Towards Cost-effective Specialization for Chiplet-based Spatial Accelerators
by: Hao, Xiaochen, et al.
Published: (2023)

ChipletPart: Cost-Aware Partitioning for 2.5D Systems
by: Graening, Alexander, et al.
Published: (2025)

RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule
by: Tang, Jiaping, et al.
Published: (2025)

MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures
by: Pfromm, Lukas, et al.
Published: (2024)

The Survey of Chiplet-based Integrated Architecture: An EDA perspective
by: Chen, Shixin, et al.
Published: (2024)

THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures
by: Kanani, Alish, et al.
Published: (2025)

Mozart: Modularized and Efficient MoE Training on 3.5D Wafer-Scale Chiplet Architectures
by: Luo, Shuqing, et al.
Published: (2026)

Hemlet: A Heterogeneous Compute-in-Memory Chiplet Architecture for Vision Transformers with Group-Level Parallelism
by: Wang, Cong, et al.
Published: (2025)

On the Vulnerability of FHE Computation to Silent Data Corruption
by: Mu, Jianan, et al.
Published: (2026)

Hecaton: Training Large Language Models with Scalable Chiplet Systems
by: Huang, Zongle, et al.
Published: (2024)

Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures enabled by Non-bendable Glass Interposer
by: Sharma, Harsh, et al.
Published: (2025)

LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow
by: Chang, Kaiyan, et al.
Published: (2025)

Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles
by: Narashiman, Swathi, et al.
Published: (2024)

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
by: Sudarshan, Chetan Choppali, et al.
Published: (2023)

Chiplet-Gym: Optimizing Chiplet-based AI Accelerator Design with Reinforcement Learning
by: Mishty, Kaniz, et al.
Published: (2024)

Analysis of LLM Vulnerability to GPU Soft Errors: An Instruction-Level Fault Injection Study
by: Chai, Duo, et al.
Published: (2025)

Mapping Space Exploration for Multi-Chiplet Accelerators Targeting LLM Inference Serving Workloads
by: Li, Boyu, et al.
Published: (2025)

Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
by: Yu, Zhongkai, et al.
Published: (2024)

Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim
by: Ali, Wajid, et al.
Published: (2025)

HLSPilot: LLM-based High-Level Synthesis
by: Xiong, Chenwei, et al.
Published: (2024)

FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
by: Iff, Patrick, et al.
Published: (2025)

InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning
by: Sun, Bin, et al.
Published: (2025)

DS2SC-Agent: A Multi-Agent Automated Pipeline for Rapid Chiplet Model Generation
by: Wu, Yiwei, et al.
Published: (2026)

A Novel Cost-Effective MIMO Architecture with Ray Antenna Array for Enhanced Wireless Communication Performance
by: Dong, Zhenjun, et al.
Published: (2025)

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators
by: Das, Abhijit, et al.
Published: (2022)

Link Quality Aware Pathfinding for Chiplet Interconnects
by: Yen, Aaron, et al.
Published: (2026)

Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models
by: Peng, Huwan, et al.
Published: (2023)

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
by: Iff, Patrick, et al.
Published: (2025)

ApproxPilot: A GNN-based Accelerator Approximation Framework
by: Zhang, Qing, et al.
Published: (2024)

PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration
by: Chong, Yue Jiet, et al.
Published: (2025)

ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification
by: Monfared, Saleh Khalaj, et al.
Published: (2025)

Mozart: A Chiplet Ecosystem-Accelerator Codesign Framework for Composable Bespoke Application Specific Integrated Circuits
by: Jin, Haoran, et al.
Published: (2025)

Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
by: Scheffler, Paul, et al.
Published: (2025)